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参数资料
| 型号： | IDT70T3799MS166BBGI |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 高速与3.3V 2.5V的256/128K × 72 SYNCHRONOU S双，端口静态RAM或2.5V的接口 |
| 文件页数： | 22/25页 |
| 文件大小： | 316K |
| 代理商： | IDT70T3799MS166BBGI |
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Advanced
22
Figure 4. Depth and Width Expansion with IDT70T3719/99M
NOTE:
1. A
18
is for IDT70T3719, A
17
is for IDT70T3799.
5687 drw 23
IDT70T3719/99M
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
18
/A
17(1)
CE
1
CE
0
V
DD
V
DD
IDT70T3719/99M
IDT70T3719/99M
IDT70T3719/99M
Control Inputs
Control Inputs
Control Inputs
Control Inputs
BE
,
R/
W
,
OE
,
CLK,
ADS
,
REPEAT
,
CNTEN
,
Depth and Width Expansion
The IDT70T3719/99Mfeatures dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3719/99Mcan also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 144-bits.
Register Sizes, and SystemInterface Parameter tables. Specifically,
commands for Array B must precede those for Array A in any JTAG
operations sent to the IDT70T3719/99M Please reference Application
Note AN-411, "JTAG Testing of Multichip Modules" for specific instruc-
tions on performng JTAG testing on the IDT70T3719/99M. AN-411 is
available at www.idt.com
Array A
Array B
TCK
TMS
TRST
TDI
TDOA
TDIB
TDO
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IDT70T3719/99M
Figure 5. JTAG Configuration for IDT70T3719/99M
J TAG Functionality and Configuration
The IDT70T3719/99Mis composed of two independent memory
arrays, and thus cannot be treated as a single JTAG device in the scan
chain. The two arrays (A and B) each have identical characteristics and
commands but must be treated as separate entities in JTAG operations.
Please refer to Figure 5.
JTAG signaling must be provided serially to each array and utilize the
information provided in the Identification Register Definitions, Scan
.
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| IDT70T631S10BC | 功能描述:IC SRAM 4MBIT 10NS 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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| IDT70T631S10BCI8 | 功能描述:IC SRAM 4MBIT 10NS 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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