参数资料
型号: IDT70T633S12BF
厂商: IDT, Integrated Device Technology Inc
文件页数: 17/27页
文件大小: 0K
描述: IC SRAM 9MBIT 12NS 208FBGA
标准包装: 7
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 9M(512K x 18)
速度: 12ns
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 托盘
其它名称: 70T633S12BF
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH ) (2,4,5)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
(1)
t APS
t DW
VALID
t DH
ADDR "B"
MATCH
t BAA
BUSY "B"
t WDD
DATA OUT "B"
t DDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE).
2. CE 0L = CE 0R = V IL ; CE 1L = CE 1R = V IH .
3. OE = V IL for the reading port.
4. If M/ S = V IL (slave), BUSY is an input. Then for this example BUSY "A" = V IH and BUSY "B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/ S = V IL )
t WP
R/ W "A"
t WB (3)
t BDA
t BDD
VALID
5670 drw 14
.
BUSY "B"
R/ W "B"
(2)
t WH
(1)
NOTES:
1. t WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB only applies to the slave mode.
17
5670 drw 15
.
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