参数资料
型号: IDT70V05L15JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/22页
文件大小: 0K
描述: IC SRAM 64KBIT 15NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 15ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
其它名称: 70V05L15JG
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,3,5,8)
t WC
ADDRESS
OE
t AW
t HZ
(7)
CE
or SEM
(9)
t WR
t AS (6)
t WP
(2)
(3)
R/ W
t WZ (7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
DATA IN
2941 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,3,5,8)
t WC
ADDRESS
t AW
CE or SEM
(9)
t AS
(6)
t EW
(2)
t WR (3)
R/ W
t DW
t DH
DATA IN
2941 drw 09
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a LOW CE and a LOW R/ W for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W ) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE , or R/ W .
7. Timing depends on which enable signal is de-asserted first, CE , or R/ W .
8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t DW . If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
9. To access RAM, CE = V IL and SEM = V IH . To access Semaphore, CE = V IH and SEM = V IL . t EW must be met for either condition.
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