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参数资料
| 型号： | IDT70V06S20J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 19/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 20NS 68PLCC |
| 标准包装： | 250 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K (16K x 8) |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24x24） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70V06S20J8 |
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
MASTER
CE
SLAVE
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
Dual Port
SRAM
BUSY (L) BUSY (R)
MASTER
Dual Port
CE
SLAVE
Dual Port
CE
BUSY (L)
SRAM
BUSY (L) BUSY (R)
SRAM
BUSY (L) BUSY (R)
BUSY (R)
,
2942 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 SRAMs.
allows one of the two accesses to proceed and signals the other side that
the SRAM is “busy”. The BUSY pin can then be used to stall the access
until the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of an
illegal or illogical operation. If the write inhibit function of BUSY logic is not
desirable, the BUSY logic can be disabled by placing the part in slave mode
with the M/ S pin. Once in slave mode the BUSY pin operates solely as
a pin. Normal operation can be programmed by tying the BUSY pins HIGH.
If desired, unintended write operations can be prevented to a port by tying
the BUSY pin for that port LOW.
The BUSY outputs on the IDT 70V06 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the busy indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V06 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the SRAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the BUSY signal as a write inhibit signal. Thus on the IDT70V06 RAM the
BUSY pin is an output if the part is used as a master (M/ S pin = V IH ), and
the BUSY pin is an input if the part used as a slave (M/ S pin = V IL ) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for part of
the other word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/ W signal. Failure to observe this timing
can result in a glitched internal write inhibit signal and corrupted data in the
slave.
Semaphores
The IDT70V06 is an extremely fast Dual-Port 16K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port SRAM or any other shared
resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
down feature controlled by CE , the Dual-Port SRAM enable, and SEM ,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
I where CE and SEM are both HIGH.
Systems which can best use the IDT70V06 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V06's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V06 does not use its semaphore flags
19
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| IDT70V06S20PF | 功能描述:IC SRAM 128KBIT 20NS 64TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT70V06S20PF8 | 功能描述:IC SRAM 128KBIT 20NS 64TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
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| IDT70V06S25J | 功能描述:IC SRAM 128KBIT 25NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT70V06S25J8 | 功能描述:IC SRAM 128KBIT 25NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
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