参数资料
型号: IDT70V07S35J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/19页
文件大小: 0K
描述: IC SRAM 256KBIT 35NS 68PLCC
标准包装: 250
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K (32K x 8)
速度: 35ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 带卷 (TR)
其它名称: 70V07S35J8
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
____
____
____
____
25
25
25
25
____
____
____
____
35
35
35
35
____
____
____
____
45
45
45
45
ns
ns
ns
ns
BUSY Disable to Valid Data
t APS
t BDD
Arbitration Priority Set-up Time
(3)
(2)
5
____
____
35
5
____
____
40
5
____
____
50
ns
ns
BUSY TIMING (M/ S - V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
20
____
____
0
25
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
t DDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay (1)
____
____
55
50
____
____
65
60
____
____
85
80
ns
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY ".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY (2,4,5)
t WC
2943 tbl 13
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t DW
VALID
t DH
ADDR "B"
t APS
(1)
MATCH
BUSY "B"
DATA OUT "B"
t BAA
t WDD
t BDA
t BDD
VALID
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE).
t DDD
(3)
2943 drw 13
2. CE L = CE R = V IL
3. OE = V IL for the reading port.
4. If M/ S = V IL (SLAVE), then BUSY is an input ( BUSY "A" = V IH and BUSY "B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
11
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