参数资料
型号: IDT70V38L20PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/17页
文件大小: 0K
描述: IC SRAM 1.125MBIT 20NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(64K x 18)
速度: 20ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 70V38L20PF8
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/ S = V IH ) (1,3)
ADDR "A"
and "B"
CE "A"
CE "B"
t APS (2)
ADDRESSES MATCH
t BAC
t BDC
BUSY "B"
4850 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/ S = V IH ) (1)
ADDR "A"
ADDR "B"
ADDRESS "N"
t APS (2)
MATCHING ADDRESS "N"
BUSY "B"
t BAA
t BDA
,
4850 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V38L15
Com'l Only
70V38L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
15
15
0
0
____
____
____
____
20
20
ns
ns
ns
ns
4850 tbl 15
12
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