参数资料
型号: IDT70V631S10BC
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/23页
文件大小: 0K
描述: IC SRAM 4MBIT 10NS 256BGA
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 4.5M(256K x 18)
速度: 10ns
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70V631S10BC
800-2314
IDT70V631S10BC-ND
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
Parameter
70V631S10
Com'l Only
Min. Max.
70V631S12
Com'l
& Ind
Min. Max.
70V631S15
Com'l
Min. Max.
Unit
BUSY TIMING (M/ S =V IH )
BUSY Disable to Valid Data
Write Hold After BUSY
t BAA
t BDA
t BAC
t BDC
t APS
t BDD
t WH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time (2)
(3)
(5)
____
____
____
____
5
____
8
10
10
10
10
____
10
____
____
____
____
____
5
____
10
12
12
12
12
____
12
____
____
____
____
____
5
____
12
15
15
15
15
____
15
____
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/ S =V IL )
t WB
t WH
BUSY Input to Write (4)
Write Hold After BUSY (5)
0
8
____
____
0
10
____
____
0
12
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
t DDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay (1)
____
____
22
20
____
____
25
22
____
____
30
25
ns
ns
NOTES:
5622 tbl 14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of the Max. spec, t WDD – t WP (actual), or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
14
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