参数资料
型号: IDT70V657S15BC8
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/24页
文件大小: 0K
描述: IC SRAM 1.125MBIT 15NS 256BGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(32K x 36)
速度: 15ns
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 带卷 (TR)
其它名称: 70V657S15BC8
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (V DD = 3.3V ± 150mV)
70V659/58/57S
Input Leakage Current
Symbol
|I LI |
|I LO |
Parameter
(1)
Output Leakage Current
Test Conditions
V DDQ = Max., V IN = 0V to V DDQ
CE 0 = V IH or CE 1 = V IL , V OUT = 0V to V DDQ
Min.
___
___
Max.
10
10
Unit
μA
μA
V OL (3.3V)
Output Low Voltage
(2)
I OL = +4mA, V DDQ = Min.
___
0.4
V
V OH (3.3V)
V OL (2.5V)
Output High Voltage (2)
Output Low Voltage (2)
I OH = -4mA, V DDQ = Min.
I OL = +2mA, V DDQ = Min.
2.4
___
___
0.4
V
V
V OH (2.5V)
Output High Voltage
(2)
I OH = -2mA, V DDQ = Min.
2.0
___
V
NOTE:
4869 tbl 09
1. At V DD < - 2.0V input leakages are undefined.
2. V DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (3) (V DD = 3.3V ± 150mV)
70V659/58/57S10 70V659/58/57S12 70V659/58/57S15
Com'l Only
Com'l
& Ind
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ. (4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
I DD
Dynamic Operating
CE L and CE R = V IL ,
COM'L
S
340
500
315
465
300
440
mA
Current (Both
Outputs Disabled
Ports Active)
f = f MAX (1)
IND
S
____
____
365
515
350
490
I SB1
Standby Current
CE L = CE R = V IH
COM'L
S
115
165
90
125
75
100
mA
(Both Ports - TTL
f = f MAX (1)
Level Inputs)
IND
S
____
____
115
150
100
125
CE "A" = V IL and CE "B" = V IH
I SB2
Standby Current
(5)
COM'L
S
225
340
200
325
175
315
mA
(One Port - TTL
Active Port Outputs Disabled,
Level Inputs)
f=f MAX (1)
IND
S
____
____
225
365
200
350
I SB3
I SB4
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Full Standby Current
(One Port - CMOS
Both Ports CE L and
CE R > V DDQ - 0.2V,
V IN > V DDQ - 0.2V or V IN < 0.2V,
f = 0 (2)
CE "A" < 0.2V and
CE "B" > V DDQ - 0.2V (5)
COM'L
IND
COM'L
S
S
S
3
____
220
15
____
335
3
6
195
15
15
320
3
6
170
15
15
310
mA
mA
Level Inputs)
V IN > V DDQ - 0.2V or V IN < 0.2V,
Active Port, Outputs Disabled,
f = f MAX (1)
IND
S
____
____
220
360
195
345
NOTES:
4869 tbl 10
1. At f = f MAX , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC , using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V DD = 3.3V, T A = 25°C for Typ, and are not production tested. I DD DC (f=0) = 120mA (Typ).
5. CE X = V IL means CE 0X = V IL and CE 1X = V IH
CE X = V IH means CE 0X = V IH or CE 1X = V IL
CE X < 0.2V means CE 0X < 0.2V and CE 1X > V DDQ - 0.2V
CE X > V DDQ - 0.2V means CE 0X > V DDQ - 0.2V or CE 1X - 0.2V
"X" represents "L" for left port or "R" for right port.
9
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