参数资料
型号: IDT70V7319S133BF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/21页
文件大小: 0K
描述: IC SRAM 4MBIT 133MHZ 208FBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 4.5M(256K x 18)
速度: 133MHz
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 带卷 (TR)
其它名称: 70V7319S133BF8
HIGH-SPEED 3.3V 256K x 18
Features:
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7319S
256K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
– 64 independent 4K x 18 banks
– 4 megabits of memory on chip
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MH
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/ FT L
OPT L
CLK L
ADS L
CNTEN L
REPEAT L
PL/ FT R
OPT R
CLK R
ADS R
CNTEN R
REPEAT R
R/ W L
CE 0L
CE 1L
UB L
LB L
OE L
CONTROL
LOGIC
MUX
4Kx18
MEMORY
ARRAY
(BANK 0)
CONTROL
LOGIC
R/ W R
CE 0R
CE 1R
UB R
LB R
OE R
MUX
I/O 0L-17L
I/O
CONTROL
MUX
I/O
CONTROL
I/O 0R-17R
4Kx18
MEMORY
ARRAY
A 11L
A 0L
ADDRESS
DECODE
(BANK 1)
MUX
ADDRESS
DECODE
A 11R
A 0R
BA 5L
BA 4L
BA 5R
BA 4R
BA 3L
BA 2L
BA 1L
BA 0L
BANK
DECODE
MUX
BANK
DECODE
BA 3R
BA 2R
BA 1R
BA 0R
4Kx18
MEMORY
ARRAY
(BANK 63)
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
TDI
TDO
MUX
JTAG
TMS
TCK
TRST
5629 drw 01
,
APRIL 2010
1
?2010 Integrated Device Technology, Inc.
DSC 5629/9
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