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参数资料
| 型号： | IDT70V7319S200BC8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 4MBIT 200MHZ 256BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 4.5M（256K x 18） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-CABGA（17x17） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70V7319S200BC8 |
IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Pin Names
Industrial and Commercial Temperature Ranges
Left Port
CE 0L , CE 1L
R/ W L
OE L
BA 0L - BA 5L
A 0L - A 11L
I/O 0L - I/O 17L
CLK L
PL/ FT L
ADS L
Right Port
CE 0R , CE 1R
R/ W R
OE R
BA 0R - BA 5R
A 0R - A 11R
I/O 0R - I/O 17R
CLK R
PL/ FT R
ADS R
Names
Chip Enables
Read/Write Enable
Output Enable
Bank Address (4)
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
CNTEN L
REPEAT L
LB L , UB L
V DDQL
OPT L
CNTEN R
REPEAT R
LB R , UB R
V DDQR
OPT R
V DD
V SS
TDI
TDO
TCK
Counter Enable
Counter Repeat (3)
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V) (1)
Option for selecting V DDQX (1,2)
Power (3.3V) (1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
NOTES:
1. V DD , OPT X , and V DDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT X selects the operating voltage levels for the I/Os and controls on that port.
If OPT X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V DDQX must be supplied at 3.3V. If OPT X is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V DDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEAT X is asserted, the counter will reset to the last valid address loaded
via ADS X .
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA 0L - BA 5L ≠ BA 0R - BA 5R ). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
TMS
TRST
Test Mode Select
Reset (Initialize TAP Controller)
5629 tbl 01
6.42
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
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| IDT70V7339S133BCI8 | 功能描述:IC SRAM 9MBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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