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| 型号： | IDT70V7339S166DDI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 9MBIT 166MHZ 144TQFP |
| 产品变化通告： | Product Discontinuation 20/Aug/2008 |
| 标准包装： | 6 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 9M（512K x 18） |
| 速度： | 166MHz |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 144-LQFP 裸露焊盘 |
| 供应商设备封装： | 144-TQFP（20x20） |
| 包装： | 托盘 |
| 其它名称： | 70V7339S166DDI |
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control (1,2,3,4)
Upper Byte
Lower Byte
OE 3
X
X
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE 0
H
X
L
L
L
L
L
L
L
X
CE 1
X
L
H
H
H
H
H
H
H
X
UB
X
X
H
H
L
L
H
L
L
X
LB
X
X
H
L
H
L
L
H
L
X
R/ W
X
X
X
L
L
L
H
H
H
X
I/O 9-17
High-Z
High-Z
High-Z
High-Z
D IN
D IN
High-Z
D OUT
D OUT
High-Z
I/O 0-8
High-Z
High-Z
High-Z
D IN
High-Z
D IN
D OUT
High-Z
D OUT
High-Z
MODE
Deselected–Power Down
Deselected–Power Down
All Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to both Bytes
Read Lower Byte Only
Read Upper Byte Only
Read both Bytes
Outputs Disabled
NOTES:
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. ADS , CNTEN , REPEAT are set as appropriate for address access. Refer to Truth Table II for details.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address and Address Counter Control (1,2,7)
5628 tbl 02
Previous
Addr
L
L
L
Address
An
X
X
X
Address
X
An
An + 1
X
Used
An
An + 1
An + 1
An
CLK
↑
↑
↑
↑
ADS
(4)
H
H
X
CNTEN
X
(5)
H
X
REPEAT (6)
H
H
H
(4)
I/O (3)
D I/O (n)
D I/O (n+1)
D I/O (n+1)
D I/O (0)
MODE
External Address Used
Counter Enabled —Internal Address generation
External Addre ss Blocked —Counter disabled (An + 1 reused)
Counter Set to last valid ADS load
NOTES:
5628 tbl 03
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/ W , CE 0 , CE 1 , UB / LB and OE .
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE 0 , CE 1 and UB / LB
5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE 0 , CE 1 , UB / LB .
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS . This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timing Waveform of Counter Repeat, page 17. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA 0L
- BA 5L ≠ BA 0R - BA 5R ), as this condition will invalidate the access for both ports. Please refer to the functional description on page 18 for details.
5
6.42
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