参数资料
型号: IDT71024S25TYGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/8页
文件大小: 0K
描述: IC SRAM 1MBIT 25NS 32SOJ
标准包装: 23
格式 - 存储器: RAM
存储器类型: SRAM - 异步
存储容量: 1M (128K x 8)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 32-BSOJ
供应商设备封装: 32-SOJ
包装: 管件
其它名称: 71024S25TYGI
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1
( WE Controlled Timing) (1,4,6)
Timing Waveform of Write Cycle No. 2
( CS 1 AND CS 2 Controlled Timing) (1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS 1 , HIGH CS 2 , and a LOW WE .
2. t WR is measured from the earlier of either CS 1 or WE going HIGH or CS 2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS 1 LOW transition or the CS 2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS 1 and CS 2 must
both be active during the t CW write period.
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t WP must be greater than or equal to t WHZ + t DW to allow the I/O drivers to turn off and data to be placed
on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t WP .
6.42
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