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参数资料
| 型号： | IDT7130LA55TF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 8KBIT 55NS 64STQFP |
| 标准包装： | 1,250 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 8K (1K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7130LA55TF8 |
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (7)
7130X20 (1)
7140X20 (1)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT 7130)
t BAA
t BDA
t BAC
t BDC
t WH
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY (6)
____
____
____
____
12
20
20
20
20
____
____
____
____
____
15
20
20
20
20
____
____
____
____
____
20
20
20
20
20
____
ns
ns
ns
ns
ns
t WDD
Write Pulse to Data Delay
(2)
____
40
____
50
____
60
ns
BUSY Disable to Valid Data
t DDD
t APS
t BDD
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time (3)
(4)
(2)
____
5
____
30
____
25
____
5
____
35
____
35
____
5
____
35
____
35
ns
ns
ns
BUSY INPUT TIMING (For SLAVE IDT 7140)
t WB
t WH
Write to BUSY Input (5)
Write Hold After BUSY (6)
0
12
____
____
0
15
____
____
0
20
____
____
ns
ns
t WDD
Write Pulse to Data Delay
(2)
____
40
____
50
____
60
ns
t DDD
Write Data Valid to Read Data Delay (2)
____
30
____
35
____
35
ns
2689 tbl 11a
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT 7130)
t BAA
t BDA
t BAC
t BDC
t WH
BUSY Access Time from Address]
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY (6)
____
____
____
____
20
30
30
30
30
____
____
____
____
____
20
50
50
50
50
____
ns
ns
ns
ns
ns
t WDD
Write Pulse to Data Delay
(2)
____
80
____
120
ns
t DDD
t APS
t BDD
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time (3)
BUSY Disable to Valid Data (4)
(2)
____
5
____
55
____
55
____
5
____
100
____
65
ns
ns
ns
BUSY INPUT TIMING (For SLAVE IDT 7140)
t WB
t WH
Write to BUSY Input (5)
Write Hold After BUSY (6)
0
20
____
____
0
20
____
____
ns
ns
t WDD
Write Pulse to Data Delay
(2)
____
80
____
120
ns
t DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100
ns
NOTES:
1. PLCC, TQFP and STQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY ."
3. To ensure that the earlier of the two ports wins.
4. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. 'X' in part numbers indicates power rating (S or L).
14
2689 tbl 11b
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