参数资料
型号: IDT7133SA45J
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/17页
文件大小: 0K
描述: IC SRAM 32KBIT 45NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 32K(2K x 16)
速度: 45ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
其它名称: 7133SA45J
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
IDT7133SA/LA
IDT7143SA/LA
High-speed access
Low-power operation
Versatile control for write: separate write control for lower
Features
– Military: 35/55/70/90ns (max.)
– Industrial: 25/55ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
and upper byte of each port
Functional Block Diagram
R/ W LUB
CE L
R/ W LLB
OE L
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
BUSY output flag on IDT7133; BUSY input on IDT7143
Fully asynchronous operation from either port
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/ W RUB
CE R
R/ W RLB
OE R
BUSY R
I/O 8L - I/O 15L
I/O 0L - I/O 7L
BUSY L (1)
I/O
CONTROL
I/O
CONTROL
I/O 8R - I/O 15R
I/O 0R - I/O 7R
(1)
A 10L
A 0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A 10R
A 0R
11
11
CE L
ARBITRATION
LOGIC
CE R
(IDT7133 ONLY)
2746 drw 01
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
JANUARY 2012
1
?2013 Integrated Device Technology, Inc.
DSC 2746/14
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