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参数资料
| 型号： | IDT71342LA25PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/14页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 25NS 64TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K (4K x 8) |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71342LA25PF8 |
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores–Some
examples
Perhaps the simplest application of semaphores is their application
as resource markers for the IDT71342’s Dual-Port RAM. Say the 4K
x 8 RAM was to be divided into two 2K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of the memory.
To take a resource, in this example the lower 2K of Dual-Port RAM,
the processor on the left port could write and then read a zero into
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 2K. Meanwhile, the right processor would attempt to
perform the same function. Since this processor was attempting to
gain control of the resource after the left processor, it would read back
a one in response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain control of the
second 2K section by writing, then reading a zero into Semaphore 1.
If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
L PORT
SEMAPHORE
REQUEST FLIP FLOP
Industrial and Commercial Temperature Ranges
two processors to swap 2K blocks of Dual-Port RAM with each other.
The blocks do not have to by any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port RAM or other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices had determined
which memory area was “off limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously
without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby
guaranteeing a consistent data structure.
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D 0
D
Q
Q
D
D 0
WRITE
SEMAPHORE
READ
Figure 3. IDT71342 Semaphore Logic
13
6.42
WRITE
SEMAPHORE
READ
2721 drw 14
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71342LA25PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 25NS 64TQFP |
| IDT71342LA25PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 25NS 64TQFP |
| IDT71342LA25PFI | 功能描述:IC SRAM 32KBIT 25NS 64TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71342LA25PFI8 | 功能描述:IC SRAM 32KBIT 25NS 64TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71342LA35J | 功能描述:IC SRAM 32KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
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