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参数资料
| 型号： | IDT7143SA90PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 90 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 9/16页 |
| 文件大小： | 140K |
| 代理商： | IDT7143SA90PF |
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
%*.5*
.$-123
(!
NOTES:
1. Transition is measured 0mV fromLow or High-impedance voltage fromthe Output Test Load (Figure 2).
2.
This parameter is guaranteed by device characterization but not production tested.
3.
For MASTER/SLAVE combination, t
WC
= t
BAA
+ t
WR
+ t
WP
, since R/
W
= V
IL
must occur after t
BAA.
4.
The specification for t
DH
must be met by the device supplying write data to the RAMunder all operation conditions. Although t
DH
and t
OW
values will very over voltage and
temperature, the actual t
DH
will always be smaller than the actual t
OW
.
5.
'X' in part number indicates power rating (SA or LA).
Symbol
Parameter
7133X20
7143X20
Com'l Only
7133X25
7143X25
Com'l, Ind
& Mlitary
7133X35
7143X35
Com'l, Ind
& Mlitary
Unit
Mn.
Max.
Mn.
Max.
Mn.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
(3)
20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write
15
____
20
____
25
____
ns
t
AW
Address Valid to End-of-Write
15
____
20
____
25
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
15
____
20
____
25
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
15
____
15
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
20
ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
12
____
15
____
20
ns
t
OW
Output Active fromEnd-of-Write
(1,2,4)
0
____
0
____
0
____
ns
2746 tbl 11a
Symbol
Parameter
7133X45
7143X45
Com'l &
Mlitary
7133X55
7143X55
Com'l, Ind
& Mlitary
7133X70/90
7143X70/90
Com'l &
Mlitary
Unit
Mn.
Max.
Mn.
Max.
Mn.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
(3)
45
____
55
____
70/90
____
ns
t
EW
Chip Enable to End-of-Write
30
____
40
____
50/50
____
ns
t
AW
Address Valid to End-of-Write
30
____
40
____
50/50
____
ns
t
AS
Address Set-up Time
0
____
0
____
0/0
____
ns
t
WP
Write Pulse Width
30
____
40
____
50/50
____
ns
t
WR
Write Recovery Time
0
____
0
____
0/0
____
ns
t
DW
Data Valid to End-of-Write
20
____
25
____
30/30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
20
____
25/25
ns
t
DH
Data Hold Time
(4)
5
____
5
____
5/5
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
20
____
20
____
25/25
ns
t
OW
Output Active fromEnd-of-Write
(1,2,4)
5
____
5
____
5/5
____
ns
2746 tbl 11b
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