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参数资料
| 型号： | IDT7143SA90PFB |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 90 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 12/16页 |
| 文件大小： | 140K |
| 代理商： | IDT7143SA90PFB |
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
2746 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
MATCH
t
WP
R/
W
"A"
DATA
IN"A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(4)
t
WDD
DATA
OUT "B"
$858*;;,--
BUSY
!
$858*
BUSY
!
NOTES:
1. t
WH
must be met for both
BUSY
input (IDT7143, slave) and output (IDT7133, master).
2.
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
3. All timng is the same for left and right ports. Port "
A
" may be either left or right port. Port "
B
" is the opposite fromport "
A
".
NOTES:
1. To ensure that the earlier of the two ports wins, t
APS
is ignored for Slave (IDT7143).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. All timng is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite fromport "A".
2746 drw 12
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH(1)
(2)
,
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