参数资料
型号: IDT71V016SA20BFGI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/9页
文件大小: 0K
描述: IC SRAM 1MBIT 20NS 48FBGA
标准包装: 2,000
格式 - 存储器: RAM
存储器类型: SRAM - 异步
存储容量: 1M (64K x 16)
速度: 20ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 48-LFBGA
供应商设备封装: 48-CABGA(7x7)
包装: 带卷 (TR)
其它名称: 71V016SA20BFGI8
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Timing Waveform of Read Cycle No. 2 (1)
t RC
ADDRESS
t AA
OE
Commercial and Industrial Temperature Ranges
t OH
t OE
t OHZ
(3)
CS
t OLZ
(3)
t CLZ
(3)
t ACS (2)
t CHZ
(3)
BHE , BLE
DATA OUT
NOTES:
t BE
(3)
t BLZ
(2)
t BHZ (3)
DATA OUT VALID
3834 drw 07
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS , BHE , or BLE transition LOW; otherwise t AA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 ( WE Controlled Timing) (1,2,4)
t WC
ADDRESS
t AW
CS
t CW
(2)
t CHZ
(5)
t BW
BHE , BLE
WE
t WP
t WR
t BHZ
(5)
t AS
(5)
t WHZ
t OW
(5)
DATA OUT
DATA IN
PREVIOUS DATA VALID
(3)
t DW
DATA IN VALID
t DH
DATA VALID
3834 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS , LOW BHE or BLE , and a LOW WE .
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t WP must be greater than or equal to t WHZ + t DW to allow the I/O drivers to turn off and data to be placed
on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t WP .
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6
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