参数资料
型号: IDT71V321L35JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/15页
文件大小: 0K
描述: IC SRAM 16KBIT 35NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 35ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY (4)
t WP
R/ W "A"
t WB (3)
BUSY "B"
t WH (1)
NOTES:
R/ W "B"
(2)
3026 drw 11
,
1. t WH must be met for both BUSY input (71V421, slave) or output (71V321, master).
2. BUSY is asserted on port 'B' blocking R/ W ' B' , until BUSY 'B' goes HIGH.
3. t WB is for the slave version (71V421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing (1)
ADDR
"A" AND "B"
CE "B"
CE "A"
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
BUSY "A"
3026 drw 12
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing (1)
t RC
OR t WC
ADDR "A"
ADDR "B"
t APS
(2)
ADDRESSES MATCH
t BAA
ADDRESSES DO NOT MATCH
t BDA
BUSY "B"
3026 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).
10
6.42
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