参数资料
型号: IDT71V321L35JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/15页
文件大小: 0K
描述: IC SRAM 16KBIT 35NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 35ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1)
71V321X25
71V421X25
Com'l & Ind
71V321X35
71V421X35
Com'l & Ind
71V321X55
71V421X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
25
25
0
0
____
____
____
____
25
25
0
0
____
____
____
____
45
45
ns
ns
ns
ns
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Interrupt Mode (1)
SET INT
t WC
3026 tbl 12
ADDR "A"
INTERRUPT ADDRESS
t AS (3)
(2)
t WR (4)
R/ W "A"
t INS (3)
INT "B"
3026 drw 14
CLEAR INT
t RC
ADDR "B"
INTERRUPT CLEAR ADDRESS (2)
t AS (3)
OE "B"
t INR (3)
INT "B"
NOTES: .
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
11
6.42
3026 drw 15
,
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