参数资料
型号: IDT71V3557S80PFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/28页
文件大小: 0K
描述: IC SRAM 4MBIT 80NS 100TQFP
标准包装: 72
格式 - 存储器: RAM
存储器类型: SRAM - 同步 ZBT
存储容量: 4.5M(128K x 36)
速度: 80ns
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 71V3557S80PFG
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT? Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration ? 256K x 18
Absolute Maximum Ratings (1)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Symbol
V TERM (2)
Rating
Terminal Voltage with
Respect to GND
Commercial &
Industrial Values
-0.5 to +4.6
Unit
V
NC
NC
1
2
80
79
A 10
NC
V TERM (3,6)
Terminal Voltage with
-0.5 to V DD
V
NC
V DDQ
3
4
78
77
NC
V DDQ
Respect to GND
V SS
NC
NC
I/O 8
I/O 9
V SS
V DDQ
5
6
7
8
9
10
11
76
75
74
73
72
71
70
V SS
NC
I/O P1
I/O 7
I/O 6
V SS
V DDQ
V TERM (4,6)
V TERM (5,6)
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
-0.5 to V DD +0.5
-0.5 to V DDQ +0.5
V
V
I/O 10
I/O 11
V SS (1)
V DD
V DD (2)
V SS
12
13
14
15
16
17
69
68
67
66
65
64
I/O 5
I/O 4
V SS
V SS (1)
V DD
V SS/ZZ (1,4)
T A
(7)
Commercial
Operating Temperature
Industrial
-0 to +70
-40 to +85
o
o
C
C
I/O 12
I/O 13
18
19
63
62
I/O 3
I/O 2
Operating Temperature
V DDQ
V SS
I/O 14
20
21
22
61
60
59
V DDQ
V SS
I/O 1
T BIAS
Temperature
Under Bias
-55 to +125
o
C
I/O 15
23
58
I/O 0
C
I/O P2
NC
V SS
V DDQ
NC
24
25
26
27
28
57
56
55
54
53
NC
NC
V SS
V DDQ
NC
,
T STG
P T
Storage
Temperature
Power Dissipation
-55 to +125
2.0
o
W
NC
29
52
NC
NC
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51
NC
I OUT
DC Output Current
50
mA
5282 drw 02a
NOTES:
5282 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
Top View
100 TQFP
NOTES:
1. Pins 14, 64, and 66 do not have to be connected directly to V SS as long as the input voltage
is < V IL .
2. Pin 16 does not have to be connected directly to V DD as long as the input voltage
is > V IH .
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V DD terminals only.
3. V DDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V DDQ during power
supply ramp up.
7. T A is the "instant on" case temperature.
100 TQFP Capacitance (1)
(T A = +25°C, F = 1.0MHZ)
Symbol Parameter (1) Conditions
Max.
Unit
119 BGA Capacitance (1)
(T A = +25°C, F = 1.0MHZ)
C IN
C I/O
Input Capacitance
I/O Capacitance
V IN = 3dV
V OUT = 3dV
5
7
pF
pF
Symbol
C IN
Parameter (1)
Input Capacitance
Conditions
V IN = 3dV
Max.
7
Unit
pF
5282 tbl 07
C I/O
I/O Capacitance
V OUT = 3dV
7
pF
119 BGA Capacitance (1)
(T A = +25°C, F = 1.0MHZ)
5282 tbl 07a
Symbol
C IN
C I/O
Parameter (1)
Input Capacitance
I/O Capacitance
Conditions
V IN = 3dV
V OUT = 3dV
Max.
TBD
TBD
Unit
pF
pF
NOTE:
5282 tb l 07b
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
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