参数资料
型号: IDT71V3558S166PFGI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/28页
文件大小: 0K
描述: IC SRAM 4MBIT 166MHZ 100TQFP
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 同步 ZBT
存储容量: 4.5M(256K x 18)
速度: 166MHz
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 71V3558S166PFGI8
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT ? Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with CHIP Enable Used
(1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A 0
X
A 1
X
X
A 2
X
X
R/ W
X
X
H
X
H
X
X
H
X
X
ADV/ LD
L
L
L
L
L
L
L
L
L
L
CE (2)
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
BW x
X
X
X
X
X
X
X
X
X
X
OE
X
X
X
X
L
X
L
X
X
L
I/O (3)
?
?
Z
Z
Q 0
Z
Q 1
Z
Z
Q 2
Comments
Deselected.
Deselected.
Address and Control meet setup
Deselected or STOP.
Address A 0 Read out. Load A 1 .
Deselected or STOP.
Address A 1 Read out. Deselected.
Address and control meet setup.
Deselected or STOP.
Address A 2 Read out. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE 1 = L, CE 2 = L and CE 2 = H. CE = H is defined as CE 1 = H, CE 2 = H or CE 2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
5281 tbl 19
Write Operation with Chip Enable Used
(1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A 0
X
A 1
X
X
A 2
X
X
R/ W
X
X
L
X
L
X
X
L
X
X
ADV/ LD
L
L
L
L
L
L
L
L
L
L
CE (2)
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
BW x
X
X
L
X
L
X
X
L
X
X
OE
X
X
X
X
X
X
X
X
X
X
I/O (3)
?
?
Z
Z
D 0
Z
D 1
Z
Z
D 2
Comments
Deselected.
Deselected.
Address and Control meet setup
Deselected or STOP.
Address D 0 Write in. Load A 1 .
Deselected or STOP.
Address D 1 Write in. Deselected.
Address and control meet setup.
Deselected or STOP.
Address D 2 Write in. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE 1 = L, CE 2 = L and CE 2 = H. CE = H is defined as CE 1 = H, CE 2 = H or CE 2 = L.
14
6.42
5281 tbl 20
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