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| 型号： | IDT71V3558SA166BQG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/28页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 4MBIT 166MHZ 165FBGA |
| 标准包装： | 136 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 4.5M（256K x 18） |
| 速度： | 166MHz |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 165-TBGA |
| 供应商设备封装： | 165-CABGA（13x15） |
| 包装： | 托盘 |
| 其它名称： | 71V3558SA166BQG |
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IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT ? Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Description continued
Commercial and Industrial Temperature Ranges
The IDT71V3556/58 has an on-chip burst counter. In the burst
mode, the IDT71V3556/58 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/ LD signal is used to load a new
Pin Definition (1)
external address (ADV/ LD = LOW) or increment the internal burst
counter (ADV/ LD = HIGH).
The IDT71V3556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball
grid array (BGA) and a 165 fine pitch ball grid array (fBGA).
Symbol
A 0 -A 17
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/ LD low, CEN low, and true chip enables.
ADV/ LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the chip
ADV/ LD
Advance / Load
I
N/A
deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled
high.
R/ W
Read / Write
I
N/A
R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
CEN
Clock Enable
I
LOW
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
BW 1 - BW 4
Individual Byte
Write Enables
I
LOW
(When R/ W and ADV/ LD are sampled low) the appropriate byte write signal ( BW 1 - BW 4 ) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is
sampled high. The appro priate byte(s) of data are written into the device two cycles later. BW 1 - BW 4 can all be
tied low if always doing write to the entire 36-bit word.
Synchronous active low chip enable. CE 1 and CE 2 are used with CE 2 to enable the IDT71V3556/58. ( CE 1 or
CE 1 , CE 2
CE 2
CLK
I/O 0 -I/O 31
I/O P1 -I/O P4
LBO
Chip Enables
Chip Enable
Clock
Data Input/Output
Linear Burst Order
I
I
I
I/O
I
LOW
HIGH
N/A
N/A
LOW
CE 2 sampled high or CE 2 sampled low) and ADV/ LD low at the rising edge of clock, initiates a deselect cycle.
The ZBT TM has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
Synchronous active high chip enable. CE 2 is used with CE 1 and CE 2 to enable the chip. CE 2 has inverted
polarity but otherwise identical to CE 1 and CE 2 .
This is the clock input to the IDT71V3556/58. Except for OE , all timing references for the device are made with
respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the I/O pins
OE
TMS
TDI
TCK
TDO
TRST
Output Enable
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset
(Optional)
I
I
I
I
O
I
LOW
N/A
N/A
N/A
N/A
LOW
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to
ZZ
Sleep Mode
I
HIGH
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
V DD
V DDQ
V SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
5281 tbl 02
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V3558SA166BQG8 | 功能描述:IC SRAM 4MBIT 166MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V3558SA166BQGI | 功能描述:IC SRAM 4MBIT 166MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:MoBL® 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并联 电源电压:2.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-VFBGA 供应商设备封装:48-VFBGA（6x8） 包装:带卷 (TR) |
| IDT71V3558SA166BQGI8 | 功能描述:IC SRAM 4MBIT 166MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V3558SA200BQG | 功能描述:IC SRAM 4MBIT 200MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:MoBL® 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并联 电源电压:2.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-VFBGA 供应商设备封装:48-VFBGA（6x8） 包装:带卷 (TR) |
| IDT71V3558SA200BQG8 | 功能描述:IC SRAM 4MBIT 200MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
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