参数资料
型号: IDT71V35761S166BQGI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/21页
文件大小: 0K
描述: IC SRAM 4MBIT 166MHZ 165FBGA
产品变化通告: Product Discontinuation 05/Nov/2008
标准包装: 2,000
格式 - 存储器: RAM
存储器类型: SRAM - 同步
存储容量: 4.5M(128K x 36)
速度: 166MHz
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
封装/外壳: 165-TBGA
供应商设备封装: 165-CABGA(13x15)
包装: 带卷 (TR)
其它名称: 71V35761S166BQGI8
128K x 36
3.3V Synchronous SRAMs
IDT71V35761YS/S
IDT71V35761YSA/SA
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
128K x 36 memory configurations
Features
Description
The IDT71V35761 are high-speed SRAMs organized as
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control ( GW ), byte write
enable ( BWE ), and byte writes ( BW x)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected ( ADV =LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
Pin Description Summary
A 0 -A 17
CE
CS 0 , CS 1
OE
GW
BWE
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
BW 1 , BW 2 , BW 3 , BW 4
CLK
ADV
ADSC
ADSP
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
(1)
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5301 tbl 01
?2010 Integrated Device Technology, Inc.
1
MAY 2010
DSC-5301/05
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