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| 型号： | IDT71V65803S100BQI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 9MBIT 100MHZ 165FBGA |
| 标准包装： | 136 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 9M（512K x 18） |
| 速度： | 100MHz |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 165-TBGA |
| 供应商设备封装： | 165-CABGA（13x15） |
| 包装： | 托盘 |
| 其它名称： | 71V65803S100BQI |
256K x 36, 512K x 18
3.3V Synchronous ZBT? SRAMs
ZBT? Feature
3.3V I/O, Burst Counter
Pipelined Outputs
IDT71V65603/Z
IDT71V65803/Z
Features
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 150MHz
ZBT TM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
Single R/ W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
4-word burst capability (interleaved or linear)
Individual byte write ( BW 1 - BW 4 ) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (V DDQ )
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
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(3.8ns Clock-to-Data Access)
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need to control OE
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signal registers for fully pipelined applications
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flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT TM , or Zero Bus Turnaround.
Pin Description Summary
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or write.
The IDT71V65603/5803 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable ( CEN ) pin allows operation of the IDT71V65603/5803 to
be suspended as long as necessary. All synchronous inputs are ignored when
( CEN ) is high and the internal device registers will hold their previous values.
There are three chip enable pins ( CE 1, CE2, CE 2) that allow the user
to deselect the device when desired. If any one of these three are not asserted
when ADV/ LD is low, no new memory operation can be initiated. However,
any pending data transfers (reads or writes) will be completed. The data bus
will tri-state two cycles after chip is deselected or a write is initiated.
The IDT71V65603/5803 have an on-chip burst counter. In the burst
mode, the IDT71V65603/5803 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/ LD signal is used to load a new
external address (ADV/ LD = LOW) or increment the internal burst counter
(ADV/ LD = HIGH).
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and
165 fine pitch ball grid array (fBGA) .
A 0 -A 18
CE 1 , CE 2 , CE 2
OE
R/ W
CEN
BW 1 , BW 2 , BW 3 , BW 4
CLK
ADV/ LD
LBO
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
1
?2007 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-5304/07
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V65803S100PF | 功能描述:IC SRAM 9MBIT 100MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V65803S100PF8 | 功能描述:IC SRAM 9MBIT 100MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V65803S100PFG | 功能描述:IC SRAM 9MBIT 100MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65803S100PFG8 | 功能描述:IC SRAM 9MBIT 100MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:MoBL® 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并联 电源电压:2.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-VFBGA 供应商设备封装:48-VFBGA（6x8） 包装:带卷 (TR) |
| IDT71V65803S100PFGI | 功能描述:IC SRAM 9MBIT 100MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
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