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参数资料
| 型号： | IDT72285L10PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/25页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 65536X18 LP 10NS 64-TQFP |
| 标准包装： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 1.1M（65K x 18） |
| 访问时间： | 10ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72285L10PF8 |
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
12
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations.Uponthecompletionofavalidreadcycle,FF
willgoHIGHallowingawritetooccur.TheFF isupdatedbytwoWCLKcycles
+ tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stoptheRCLK.NotethatwhileRCLKisidle,theEF/OR,PAEandHFflagswill
not be updated. (Note that RCLK is only capable of updating the HF flag to
HIGH.) The Write and Read Clocks can be independent or coincident.
READ ENABLE (REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister.ThedataoutputsQ0-Qnmaintain
the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
wordwrittentoanemptyFIFO,mustberequestedusingREN.Whenthelast
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
furtherreadoperations.RENisignoredwhentheFIFOisempty.Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur.TheEFflagisupdated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW
afterthefirstwrite.RENdoesnotneedtobeassertedLOW.Inordertoaccess
allotherwords,areadmustbeexecutedusingREN.TheRCLKLOWtoHIGH
transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN =LOW),inhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset.SENisalwaysusedinconjunctionwithLD.Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGH transition of WCLK. (See Figure 4.)
WhenSENisHIGH,theprogrammableregistersretainstheprevioussettings
andnooffsetsareloaded.SENfunctionsthesamewayinbothIDTStandard
and FWFT modes.
OUTPUT ENABLE (OE)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister.WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD input
determinesoneoftwodefaultoffsetvalues(127or1,023)forthePAEandPAF
flags,alongwiththemethodbywhichtheseoffsetregisterscanbeprogrammed,
parallelorserial.AfterMasterReset,LDenableswriteoperationstoandread
operationsfromtheoffsetregisters.Onlytheoffsetloadingmethodcurrently
selectedcanbeusedtowritetotheregisters.Offsetregisterscanbereadonly
inparallel.ALOWonLDduringMasterResetselectsadefaultPAEoffsetvalue
of07FH(athreshold127wordsfromtheemptyboundary),adefaultPAFoffset
value of 07FH (a threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on LD during Master Reset selects a
default PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary),adefaultPAFoffsetvalueof3FFH(athreshold1,023wordsfrom
the full boundary), and serial loading of other offset values.
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
orparallelloadorreadoftheseoffsetvalues.SeeFigure4,ProgrammableFlag
Offset Programming Sequence.
OUTPUTS:
FULL FLAG (FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 32,768 for the IDT72275 and 65,536 for the IDT72285). See Figure 7,
WriteCycleandFullFlagTiming(IDTStandardMode),fortherelevanttiming
information.
InFWFTmode,theInputReady(IR)functionisselected.IRgoesLOWwhen
memoryspaceisavailableforwritingindata.Whenthereisnolongeranyfree
space left, IR goes HIGH, inhibiting further write operations. If no reads are
performedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writesto
the FIFO (D = 32,769 for the IDT72275 and 65,537 for the IDT72285) See
Figure 9, Write Timing (FWFT Mode), for the relevant timing information.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister.Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
doubleregister-bufferedoutputs.
EMPTY FLAG (EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited until OR goes LOW
again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode,ORisatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(32,768-m)writesfortheIDT72275and
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| IDT72285L10TF | 功能描述:IC FIFO SUPSYNC 65536X18 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72285L10TF8 | 功能描述:IC FIFO 65536X18 LP 10NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72285L10TFG | 功能描述:IC FIFO 65536X18 LP 10NS 64STQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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