参数资料
型号: IDT72285L10PFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 17/25页
文件大小: 0K
描述: IC FIFO 65536X18 10NS 64TQFP
标准包装: 90
系列: 7200
功能: 同步
存储容量: 1.1M(65K x 18)
访问时间: 10ns
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 托盘
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
24
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72275
72285
TRANSFER CLOCK
4674 drw 23
n
FWFT/SI
IDT
72275
72285
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
TheIDT72275caneasilybeadaptedtoapplicationsrequiringdepthsgreater
than 32,768 and 65,536 for the IDT72285 with an 18-bit bus width. In FWFT
mode, the FIFOs can be connected in series (the data outputs of one FIFO
connectedtothedatainputsofthenext)withnoexternallogicnecessary. The
resultingconfigurationprovidesatotaldepthequivalenttothesumofthedepths
associated with each single FIFO. Figure 20, Block Diagram of 65,536 x 18
and 131,072 x 18 Depth Expansion shows a depth expansion using two
IDT72275/72285 devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down") until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
EachtimethedatawordappearsattheoutputsofoneFIFO,thatdevice'sOR
line goes LOW, enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW3
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock, for the IR flag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
end of the chain and free locations to the beginning of the chain.
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