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参数资料
| 型号： | IDT72285L10PFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/25页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 65536X18 10NS 64TQFP |
| 标准包装： | 90 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 1.1M（65K x 18） |
| 访问时间： | 10ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 托盘 |
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
10
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
andPAFproceedsasfollows:whenLDandSENaresetLOW,dataontheSI
inputarewritten,onebitforeachWCLKrisingedge,startingwiththeEmptyOffset
LSBandendingwiththeFullOffsetMSB.Atotalof30bitsfortheIDT72275and
32bitsfortheIDT72285.SeeFigure13,SerialLoadingofProgrammableFlag
Registers,forthetimingdiagramforthismode.
Usingtheserialmethod,individualregisterscannotbeprogrammedselec-
tively.PAEandPAFcanshowavalidstatusonlyafterthecompletesetofbits
(foralloffsetregisters)hasbeenentered.Theregisterscanbereprogrammed
aslongasthecompletesetofnewoffsetbitsisentered.WhenLDisLOWand
SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence.Inthiscase,theprogrammingofalloffsetbitsdoesnot
havetooccuratonce.AselectnumberofbitscanbewrittentotheSIinputand
then, by bringing LD and SENHIGH,datacanbewrittentoFIFOmemoryvia
Dnbytoggling WEN.WhenWEN isbroughtHIGHwithLDandSENrestored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW
anddeactivateSENortosetSENLOWanddeactivateLD.OnceLDandSEN
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherpartialflagwillbevalid
until the full set of bits required to fill all the offset registers has been written.
Measuring from the rising WCLK edge that achieves the above criteria; PAF
willbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalidafter
the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combinationoftheLD,WCLK,WENandDninputpins.ProgrammingPAEand
PAFproceedsasfollows:whenLDandWENaresetLOW,dataontheinputs
DnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-to-HIGHtransition
ofWCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,dataarewritten
intotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,onceagain,to
theEmptyOffsetRegister.SeeFigure14,ParallelLoadingofProgrammable
FlagRegisters,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer.Thetwopointersoperateindependently;however,areadandawrite
shouldnotbeperformedsimultaneouslytotheoffsetregisters.AMasterReset
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
noeffectonthepositionofthesepointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing LD HIGH, write operations can be redirected to
theFIFOmemory.WhenLDissetLOWagain,andWENisLOW,thenextoffset
registerinsequenceiswrittento.Asanalternativetoholding WENLOWand
togglingLD,parallelprogrammingcanalsobeinterruptedbysettingLDLOW
andtogglingWEN.
Notethatthestatusofapartialflag(PAEorPAF)outputisinvalidduringthe
programmingprocess.Fromthetimeparallelprogramminghasbegun,apartial
flagoutputwillnotbevaliduntiltheappropriateoffsetwordhasbeenwrittento
theregister(s)pertainingtothatflag.MeasuringfromtherisingWCLKedgethat
achievestheabovecriteria;PAFwillbevalidaftertwomorerisingWCLKedges
plustPAF,PAEwillbevalidafterthenexttworisingRCLKedgesplustPAEplus
tSKEW2.
The act of reading the offset registers employs a dedicated read offset
registerpointer.ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
pinswhen LD is set LOW and REN is set LOW. Data are read via Qn from the
EmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.Uponthe
second LOW-to-HIGH transition of RCLK, data are read from the Full Offset
Register.ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffset
Register. See Figure 15, Parallel Read of Programmable Flag Registers, for
thetimingdiagramforthismode.
It is permissible to interrupt the offset register read sequence with reads
or writes to the FIFO. The interruption is accomplished by deasserting REN,
LD,orbothtogether.When RENand LD arerestoredtoaLOWlevel,reading
oftheoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
the data word that was present on the output lines Qn will be overwritten.
Parallelreadingoftheoffsetregistersisalwayspermittedregardlessofwhich
timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessedagain.Therearetwostages:first,asetupprocedurethatresetsthe
read pointer to the first location of memory, then the actual retransmit, which
consistsofreadingoutthememorycontents,startingatthebeginningofmemory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
RENandWENmustbeHIGHbeforebringingRTLOW.Atleastoneword,but
nomorethanD-2wordsshouldhavebeenwrittenintotheFIFObetweenReset
(Master or Partial) and the time of Retransmit setup. D = 32,768 for the
IDT72275 and D = 65,536 for the IDT72285. In FWFT mode, D = 32,769 for
the IDT72275 and D= 65,537 for the IDT72285.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initializedtothefirstlocationoftheRAMarray.
When EF goes HIGH, Retransmit setup is complete and read operations
maybeginstartingwiththefirstlocationinmemory.SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
ForeitherIDTStandardmodeorFWFTmode,updatingofthePAE,HFand
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
thePAEflagwillbeupdated.HFisasynchronous,thustherisingedgeofRCLK
thatRTissetupwillupdateHF.PAFissynchronizedtoWCLK,thusthesecond
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT
is setup will update PAF. RT is synchronized to RCLK.
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| IDT72285L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 LP 10NS 64-TQFP |
| IDT72285L10TF | 功能描述:IC FIFO SUPSYNC 65536X18 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72285L10TF8 | 功能描述:IC FIFO 65536X18 LP 10NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72285L10TFG | 功能描述:IC FIFO 65536X18 LP 10NS 64STQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72285L15PF | 功能描述:IC FIFO 65536X18 LP 15NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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