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参数资料
| 型号： | IDT723616L20PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/26页 |
| 文件大小： | 0K |
| 描述： | IC FIFO TRPL BUS 64X36X2 128QFP |
| 标准包装： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 4.6K（64 x 36 x2） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 723616L20PF8 |
12
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
This register is loaded with one of four preset values during a device reset (see
Reset above). An Almost-Full flag is LOW when the FIFO contains (64-X) or
more long words in memory and is HIGH when the FIFO contains [64-(X+1)]
or less long words.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
are required after a FIFO read for the Almost-Full flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less
words remains LOW if two cycles of the synchronizing clock have not elapsed
since the read that reduced the number of long words in memory to [64-(X+1)].
An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the
synchronizing clock after the FIFO read that reduces the number of long words
in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag
synchronizing clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of long words in
memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 18 and 19).
BUS SIZING
Both ports B and C, taken together, may be configured for either an 18-
bit word or a 9-bit byte format, thus determining the word width of the data
read from FIFO1 or written to FIFO2. Whichever bus size is selected
appliestobothportsBandC.Itisnotpossibletoconfigurethebuswidthofports
B and C independently.
The levels applied to the bus size select (SIZ0, SIZ1) inputs must be static
through out FIFO operation. These levels can only be changed when the FIFO
is idle (no read or write activity) just preceding Master Reset operation. The
bus size as selected using SIZ0 and SIZ1 is implemented according to Figure
2. Note that neither a HIGH nor a LOW logic level should be applied to both
SIZ0 and SIZ1 at the same time; these states are reserved.
Only 36-bit long-word data is written to or read from the two FIFO memories
on the IDT723616. Bus-matching operations are done after data is read from
the FIFO1 RAM and before data is written to the FIFO2 RAM.
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. Since
Port B can only have a byte or word size, only the first one or two bytes
appear on the selected portion of the FIFO1 output register, with the rest
of the long word stored in auxiliary registers. In this case, subsequent
FIFO1 reads with the same bus size implementation output the rest of the
long word to the FIFO1 output register in the order shown by Figure 2.
When reading data from FIFO1 in byte format, the unused B0-B17
outputs remain inactive but static, with the unused FIFO1 output register
bits holding the last data value to decrease power consumption.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. Data
can be written to FIFO2 with a byte or word bus size. This action stores the
initial bytes or words in auxiliary registers. The CLKC rising edge that
writes the fourth byte or the second word of long word to FIFO2 also stores
the entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 2.
BYTE SWAPPING
The byte-order arrangement of data read from FIFO1 or data written to
FIFO2 can be changed synchronous to the rising edge of CLKB. Four
modes of byte-order swapping (including no swap) can be done with any
data port size selection. The order of the bytes are rearranged within the long
word, but the bit order within the bytes remains constant.
The swap configuration can be selected independently for ports B and C.
ThePortBSwapSelectinputs(SWB0andSWB1)areusedtochoosethebyte
arrangement for Port B. The Port C Swap Select inputs (SWC0 and SWC1)
are used to choose the byte arrangement for Port C. The levels applied to the
swap select must be static throughout FIFO operation. These levels can only
be changed when the FIFO is idle (no read or write activity) just preceding
Master Reset operation. Figures 3 and 4 are examples of the byte-order
swapping operations available for 18-bit words. Performing a byte swap and
bus size simultaneously for a FIFO1 read first rearranges the bytes as shown
in Figure 3, then outputs the bytes as shown in Figure 2. Simultaneous bus
sizing and byte swapping operations for FIFO2 writes first loads the data
according to Figure 2, then swaps the bytes as shown in Figure 4 when the
long word is loaded to FIFO2 RAM.
PARITY CHECKING
The Port A inputs (A0-A35) have four parity trees to check the parity of
incoming (or outgoing) data; the Port B inputs (B0-B17) have two parity trees
to check the parity of outgoing data; Port C inputs (C0-C17) have two parity
trees to check the parity of incoming data. A parity failure on one or more bytes
of the Port A data bus is reported by a LOW level on the port parity error flag
(
PEFA). A parity failure on one or more bytes of the Port C data bus that are
valid for the bus size implementation is reported by a LOW level on the Port
C parity error flag (PEFC). Odd or even parity checking can be selected, and
the parity error flags can be ignored if this feature is not desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheODD/
EVEN parity select input. A parity error on one or more valid bytes of a port
is reported by a LOW level on the corresponding port parity error flag (
PEFA,
PEFC) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26, and
A27-A35. Port C bytes are arranged as C0-C8 and C9-C17, and its valid bytes
are those used in a Port C bus size implementation. When ODD/
EVEN parity
is selected, a port parity error flag (
PEFA, PEFC) is LOW if any byte on the
port has an ODD/EVEN number of LOW levels applied to the bits.
PARITY GENERATION
A HIGH level on the Port A parity generate select (PGA) or Port B parity
generate select (PGB) enables the IDT723616 to generate parity bits for port
reads from a FIFO. Port A bytes are arranged as A0-A8, A9-A17, A18-26,
and A27-A35, with the most significant bit of each byte used as the parity bit.
Port B bytes are arranged as B0-B8 and B9-B17, with the most significant bit
of each byte used as the parity bit. A write to a FIFO stores the levels applied
to all nine inputs of a byte regardless of the state of the parity generate select
(PGA, PGB) inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate a parity bit
according to the level on the ODD/
EVENselect.Thegeneratedparitybitsare
substitutedforthelevelsoriginallywrittentothemostsignificantbitsofeachbyte
as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM
and before the data is written to the output register. Therefore, the Port A parity
generateselect(PGA)andODD/
EVENparityselect(ODD/EVEN)havesetup
and hold time constraints to the Port A clock (CLKA) and the Port B parity
generate select (PGB) and ODD/
EVENhavesetupandhold-timeconstraints
tothePortBclock(CLKB).Thesetimingconstraintsonlyapplyforarisingclock
edge used to read a new long word to the FIFO output register.
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参数描述 |
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| IDT723616L20PFI | 功能描述:IC FIFO TRPL BUS 64X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723616L20PFI8 | 功能描述:IC FIFO TRPL BUS 64X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723622L12PF | 功能描述:IC FIFO SYNC 256X36X2 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723622L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723622L12PQF | 功能描述:IC FIFO SYNC 256X36X2 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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