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| 型号： | IDT723673L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 8192X36 128QFP |
| 标准包装： | 36 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 288K（8K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723673L12PF |
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13
COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages.
This is done to improve flag-signal reliability by reducing the probability of
metastable events when CLKA and CLKB operate asynchronously to one
another.
FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (
EF/OR)
These are dual purpose flags. In the FWFT mode, the Output Ready (OR)
function is selected. When the Output-Ready flag is HIGH, new data is present
in the FIFO output register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
In the IDT Standard mode, the Empty Flag (
EF) function is selected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclockthat
readsdatafromitsarray(CLKB).ForboththeFWFTandIDTStandardmodes,
theFIFOreadpointerisincrementedeachtimeanewwordisclockedtoitsoutput
register. The state machine that controls an Output Ready flag monitors a write
pointerandreadpointercomparatorthatindicateswhentheFIFOmemorystatus
is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted to
the FIFO output register in a minimum of three cycles of the Output Ready flag
synchronizingclock.Therefore,anOutputReadyflagisLOWifawordinmemory
is the next data to be sent to the FlFO output register and three cycles of the port
Clock that reads data from the FIFO have not elapsed since the time the word
waswritten.TheOutputReadyflagoftheFIFOremainsLOWuntilthethirdLOW-
to-HIGHtransitionofthesynchronizingclockoccurs,simultaneouslyforcingthe
Output Ready flag HIGH and shifting the word to the FIFO output register.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flag will indicate the presence of data available for reading in a minimum of two
cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
if a word in memory is the next data to be sent to the FlFO output register and
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing
the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (
FF/IR)
This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function is
selected.InIDTStandardmode,theFullFlag(
FF)functionisselected.Forboth
timingmodes,whentheFull/InputReadyflagisHIGH,amemorylocationisfree
in the FIFO to receive new data. No memory locations are free when the Full/
Input Ready flag is LOW and attempted writes to the FIFO are ignored.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthatwrites
data to its array (CLKA). For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthantwo
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAG (
AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
data from its array (CLKB). The state machine that controls an Almost-Empty
flag monitors a write pointer and read pointer comparator that indicates when
theFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.
TheAlmost-EmptystateisdefinedbythecontentsofregisterX.Theseregisters
are loaded with preset values during a FIFO reset, programmed from Port A,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Empty flag is LOW when its FIFO contains
XorlesswordsandisHIGHwhenitsFIFOcontains(X+1)ormorewords.Note
thatadatawordpresentintheFIFOoutputregisterhasbeenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock
aftertheFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figure 15).
ALMOST-FULL FLAG (
AF)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2.TheAlmost-Fullstate
is defined by the contents of register Y. These registers are loaded with preset
values during a FlFO reset or, programmed from Port A, or programmed
serially (see Almost-Empty flag and Almost-Full flag offset programming
section). An Almost-Full flag is LOW when the number of words in its FIFO is
greater than or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT723653,
IDT723663, or IDT723673 respectively. An Almost-Full flag is HIGH when the
numberofwordsinitsFIFOislessthanorequalto[2,048-(Y+1)],[4,096-(Y+1)],
or [8,192-(Y+1)] for the IDT723653, IDT723663, or IDT723673 respectively.
Note that a data word present in the FIFO output register has been read from
memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [2,048/
4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-
HIGH transition of its synchronizing clock after the FIFO read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH
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| IDT723673L12PF8 | 功能描述:IC FIFO SYNC 8192X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723673L15PF | 功能描述:IC FIFO SYNC 8192X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723673L15PF8 | 功能描述:IC FIFO SYNC 8192X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L12PF | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L12PF8 | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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