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参数资料
| 型号： | IDT72T1845L5BBI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/55页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 2048X18 2.5V 5NS 144BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，双端口 |
| 存储容量： | 36.8K（2K x 18） |
| 数据速率： | 10MHz |
| 访问时间： | 5ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-PBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | 72T1845L5BBI |
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17
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
IDT72T18125.Ifbothx9Inputandx9OutputbusWidthsareselected,D=4,097
writes for the IDT72T1845, 8,193 writes for the IDT72T1855, 16,385 writes
for the IDT72T1865, 32,769 writes for the IDT72T1875, 65,537 writes for the
IDT72T1885, 131,073 writes for the IDT72T1895, 262,145 writes for the
IDT72T18105, 524,289 writes for the IDT72T18115 and 1,048,577 writes for
the IDT72T18125, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations,the
PAEwillgoLOWwhentherearen+1wordsintheFIFO,where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
OR will go
HIGH inhibiting further read operations.
REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125haveinternalregistersfortheseoffsets.Thereareeightdefaultoffset
valuesselectableduringMasterReset.TheseoffsetvaluesareshowninTable
2.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwoways;serial
or parallel loading method. The selection of the loading method is done using
the
LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on
LD
duringMasterResetselectsserialloadingofoffsetvalues.ALOWon
LDduring
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for
PAFand PAEflags
by use of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
not RCLK. Similarly,
PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure23forsynchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure25
for asynchronous
PAF timing and Figure 26 for asynchronous PAE timing.
(4,097-m) writes for the IDT72T1855, (8,193-m) writes for the IDT72T1865,
(16,385-m) writes for the IDT72T1875, (32,769-m) writes for the IDT72T1885,
(65,536-m)writesfortheIDT72T1895,(131,073-m)writesfortheIDT72T18105,
(262,145-m) writes for the IDT72T18115 and (524,289-m) writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D-m)
= (4,097-m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855,
(16,385-m) writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875,
(65,537-m)writesfortheIDT72T1885,(131,073-m)writesfortheIDT72T1895,
(262,145-m) writes for the IDT72T18105, (524,289-m) writes for the
IDT72T18115 and (1,048,577-m) writes for the IDT72T18125. The offset m
isthefulloffsetvalue.Thedefaultsettingforthesevaluesarestatedinthefootnote
of Table 2.
WhentheFIFOisfull,theInputReady(
IR)flagwillgoHIGH,inhibitingfurther
write operations. If no reads are performed after a reset,
IR will go HIGH after
DwritestotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,D = 2,049
writes for the IDT72T1845, 4,097 writes for the IDT72T1855, 8,193 writes for
the IDT72T1865, 16,385 writes for the IDT72T1875, 32,769 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,073 writes for the
IDT72T18105,262,145writesfortheIDT72T18115and524,289writesforthe
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
IDT72T1845
Offsets n,m
All Other
x9 to x9
*
LD
FSEL1
FSEL0
Modes
Mode
LH
L
511
L
H
255
L
127
LH
H
63
H
L
31
1,023
HH
L
15
31
HL
H
7
15
HHH
3
7
IDT72T1855, 72T1865, 72T1875, 72T1885,
72T1895, 72T18105, 72T18115, 72T18125
*
LD
FSEL1
FSEL0
Offsets n,m
H
L
1,023
LH
L
511
L
H
255
LLL
127
LH
H
63
HH
L
31
HL
H
15
HHH
7
*
LD
FSEL1
FSEL0
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
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| IDT72T1845L6-7BB | 功能描述:IC FIFO 2048X18 6-7NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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| IDT72T1855L5BBI | 功能描述:IC FIFO 4096X18 2.5V 5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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