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| 型号： | IDT72T36105L5BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/57页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 131X18 5NS 240BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 2.3K（131 x 18） |
| 数据速率： | 83MHz |
| 访问时间： | 5ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BGA |
| 供应商设备封装： | 240-PBGA（19x19） |
| 包装： | 托盘 |
| 其它名称： | 72T36105L5BB |
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22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
When a 36 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, 2 enabled read cycles are required to read
theoffsetregisters,(1peroffset).DataontheoutputsQnarereadfromtheEmpty
OffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.Uponthesecond
LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register.
ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffsetRegister.
When an 18 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 2 enabled read cycles are required to read the offset registers, (1
per offset). Data on the outputs Qn are read from the Empty Offset Register on
the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH
transitionofRCLK,dataarereadfromtheFullOffsetRegister.Thethirdtransition
of RCLK reads, once again, from the Empty Offset Register.
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Uponthe2nd LOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread
from the Empty Offset Register MSB. Upon the 3rd LOW-to-HIGH transition of
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 4th LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
theFullOffsetRegisterMSB.The5th LOW-to-HIGHtransitionofRCLKdataon
the outputs Qn are once again read from the Empty Offset Register LSB.
When a 9 bit output bus width is used:
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Uponthe2nd LOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread
from the Empty Offset Register MSB. Upon the 3rd LOW-to-HIGH transition of
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 4th LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
theFullOffsetRegisterMSB.The5th LOW-to-HIGHtransitionofRCLKdataon
the outputs Qn are once again read from the Empty Offset Register LSB.
For the IDT72T36115/72T36125, 6 enabled read cycles are required to
read the offset registers, (3 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 3rd LOW-to-HIGH transition of RCLK data on the outputs Qn are read
from the Empty Offset Register MSB. Upon the 4th LOW-to-HIGH transition of
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 6th LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
theFullOffsetRegisterMSB.The7th LOW-to-HIGHtransitionofRCLKdataon
the outputs Qn are once again read from the Empty Offset Register LSB. See
Figure 3, Programmable Flag Offset Programming Sequence. See Figure
22, Parallel Read of Programmable Flag Registers, for the timing diagram for
thismode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading of
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROM MARK OPERATION
The Retransmit from Mark feature allows FIFO data to be read repeatedly
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO
write operations from over-writing retransmit data. The retransmit data can be
readrepeatedlyanynumberoftimesfromthe‘marked’position.TheFIFOcan
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection over-
writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmit mode by a Low-
to-High transition on RCLK when the ‘MARK’ input is HIGH and
EF is HIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge
on RCLK occurs while MARK is LOW.
Once a ‘marked’ location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (
RT) is LOW. REN must be HIGH (reads disabled)
before bringing
RTLOW.Thedeviceindicatesthestartofretransmitsetupby
setting
EFLOW,alsopreventingreads.WhenEFgoesHIGH,retransmitsetup
iscompleteandreadoperationsmaybeginstartingwiththefirstdataattheMARK
location. Since IDT standard mode is selected, every word read including the
first ‘marked’ word following a retransmit setup requires a LOW on
REN(read
enabled).
Note, write operations may continue as normal during all retransmit
functions, however write operations to the ‘marked’ location will be prevented.
See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant
timingdiagram.
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
edge when the ‘MARK’ input is HIGH and
OR is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
Once a marked location has been set (and the device is still in retransmit
mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhile
the retransmit input (
RT)isLOW.RENmustbeHIGH(readsdisabled)before
bringing
RTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting
OR HIGH.
When
ORgoesLOW,retransmitsetupiscompleteandonthenextrising
RCLK edge after retransmit setup is complete, (
RTgoesHIGH),thecontents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of
REN, a
LOW on
RENisnotrequiredforthefirstword.Readingallsubsequentwords
requires a LOW on
REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
Note,theremustbeaminimumof32bytesofdatabetweenthewritepointer
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words).Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe
“marked” location until the MARK is deasserted. This prevents “overwriting”
ofretransmitdata.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce
the power consumption (in stand-by mode by utilizing the
WCS input).
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
and are purely device configuration pins.
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相关代理商/技术参数 |
参数描述 |
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| IDT72T36105L5BBI | 功能描述:IC FIFO 131X18 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T36105L6-7BB | 功能描述:IC FIFO 131X18 6-7NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T36115L10BB | 功能描述:IC FIFO 131KX36 10NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T36115L4-4BB | 功能描述:IC FIFO 131KX36 4-4NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T36115L4-4BBG | 功能描述:IC FIFO 131072X18 SYNC 240BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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