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参数资料
| 型号： | IDT72T3665L6-7BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/57页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 4096X36 6-7NS 208-BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 147K（4K x 36） |
| 数据速率： | 66MHz |
| 访问时间： | 3.8ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BGA |
| 供应商设备封装： | 208-PBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72T3665L6-7BB |
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21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds
asfollows:when
LDandSENaresetLOW,dataontheSIinputarewritten,one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 20 bits for the IDT72T3645, 22 bits for the
IDT72T3655, 24 bits for the IDT72T3665, 26 bits for the IDT72T3675, 28 bits
for the IDT72T3685, 30 bits for the IDT72T3695, 32 bits for the IDT72T36105,
34 bits for the IDT72T36115 and 36 bits for the IDT72T36125. See Figure 20,
Serial Loading of Programmable Flag Registers, for the timing diagram for this
mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling
WEN. WhenWEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOW
and deactivate
SENortosetSENLOWanddeactivateLD. OnceLDandSEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAFwillbevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalid
after the next three rising RCLK edges plus tPAE.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programming of
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceeds as follows:
LDandWENmustbesetLOW.Whenprogrammingthe
OffsetRegistersoftheTeraSyncFIFO’sthenumberofprogrammingcycleswill
be based on the bus width, the following rules apply:
When a 36 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, 2 enabled write cycles are required to
programtheoffsetregisters,(1peroffset).DataontheinputsDnarewritteninto
the Empty Offset Register on the first LOW-to-HIGH transition of WCLK. Upon
thesecondLOW-to-HIGHtransitionofWCLK,dataarewrittenintotheFullOffset
Register. The third transition of WCLK writes, once again, to the Empty Offset
Register.
When an 18 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 2 enabled write cycles are required to program the offset registers,
(1 per offset). Data on the inputs Dn are written into the Empty Offset Register
onthefirstLOW-to-HIGHtransitionofWCLK.UponthesecondLOW-to-HIGH
transition of WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset Register.
For the IDT72T36115/72T36125, 4 enabled write cycles are required to
loadtheoffsetregisters,(2peroffset).DataontheinputsDnarewrittenintothe
EmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Upon
the 2nd LOW-to-HIGH transition of WCLK data on the inputs Dn are written into
theEmptyOffsetRegisterMSB.Uponthe3rdLOW-to-HIGHtransitionofWCLK
data on the inputs Dn are written into the Full Offset Register LSB. Upon the 4th
LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheFull
OffsetRegisterMSB.The5thLOW-to-HIGHtransitionofWCLKdataontheinputs
Dn are once again written into the Empty Offset Register LSB.
When a 9 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 4 enabled write cycles are required to load the offset registers, (2
peroffset).DataontheinputsDnarewrittenintotheEmptyOffsetRegisterLSB
on the first LOW-to-HIGH transition of WCLK. Upon the 2nd LOW-to-HIGH
transitionofWCLKdataontheinputsDnarewrittenintotheEmptyOffsetRegister
MSB. Upon the 3rd LOW-to-HIGH transition of WCLK data on the inputs Dn are
written into the Full Offset Register LSB. Upon the 4th LOW-to-HIGH transition
ofWCLKdataontheinputsDnarewrittenintotheFullOffsetRegisterMSB.The
5thLOW-to-HIGHtransitionofWCLKdataontheinputsDnareonceagainwritten
into the Empty Offset Register LSB.
For the IDT72T36115/72T36125, 6 enabled write cycles are required to
loadtheoffsetregisters,(3peroffset).DataontheinputsDnarewrittenintothe
EmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Upon
the 3rd LOW-to-HIGH transition of WCLK data on the inputs Dn are written into
theEmptyOffsetRegisterMSB.Uponthe4th LOW-to-HIGHtransitionofWCLK
data on the inputs Dn are written into the Full Offset Register LSB. Upon the 6th
LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheFull
OffsetRegisterMSB.The7thLOW-to-HIGHtransitionofWCLKdataontheinputs
Dn are once again written into the Empty Offset Register LSB. See Figure 3,
Programmable Flag Offset Programming Sequence. See Figure 21, Parallel
LoadingofProgrammableFlagRegisters,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
not have to occur at one time. One, two or more offset registers can be written
and then by bringing
LDHIGH,writeoperationscanberedirectedtotheFIFO
memory. When
LDissetLOWagain,andWENisLOW,thenextoffsetregister
in sequence is written to. As an alternative to holding
WENLOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling
WEN.
Note that the status of a programmable flag (
PAEor PAF)outputisinvalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAF will be valid after
twomorerisingWCLKedgesplustPAF,
PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when
LD is set LOW and REN is set LOW. It is important to note that
consecutivereadsoftheoffsetregistersisnotpermitted.Thereadoperationmust
be disabled for a minimum of one RCLK cycle in between offset register
accesses. When reading the Offset Registers of the TeraSync FIFO’s the
number of reading cycles will be based on the bus width, the following rules
apply:
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| IDT72T3675L4-4BB | 功能描述:IC FIFO 8192X36 4-4NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T3675L5BB | 功能描述:IC FIFO 8192X36 5NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T3675L5BBI | 功能描述:IC FIFO 8192X36 5NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T3675L6-7BB | 功能描述:IC FIFO 8192X36 6-7NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T3685L4-4BB | 功能描述:IC FIFO 16384X36 4-4NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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