- 您现在的位置：买卖IC网 > PDF目录9924 > IDT72V2101L20PF8 (IDT, Integrated Device Technology Inc)IC FIFO SS 131X18 20NS 64QFP PDF资料下载
参数资料
| 型号： | IDT72V2101L20PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/27页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 131X18 20NS 64QFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 2.3K（131 x 18） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2101L20PF8 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAE and PAF values can be achieved by using a
combination of the
LD, SEN, WCLK and SI input pins. Programming PAE
and
PAF proceeds as follows: when LD and SEN are set LOW, data on the
SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 36 bits
for the IDT72V2101 and 38 bits for the IDT72V2111. See Figure 13, Serial
Loading of Programmable Flag Registers, for the timing diagram for this
mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When
LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing
LD and SEN HIGH, data can be written
to FIFO memory via Dn by toggling
WEN. When WEN is brought HIGH with
LD and SEN restored to a LOW, the next offset bit in sequence is written
to the registers via SI. If an interruption of serial programming is desired,
it is sufficient either to set
LD LOW and deactivate SEN or to set SEN LOW
and deactivate
LD. Once LD and SEN are both restored to a LOW level,
serial offset programming continues.
From the time serial programming has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria;
PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingofPAEandPAFvaluescanbeachievedbyusingacombination
of the LD, WCLK , WEN and Dn input pins.
Programming PAE and PAF proceeds as follows: when LD and WEN are
set LOW, data on the inputs Dn are written into the Empty Offset LSB Register
onthefirstLOW-to-HIGHtransitionofWCLK. UponthesecondLOW-to-HIGH
transition of WCLK, data are written into the Empty Offset Mid-Byte Register.
UponthethirdLOW-to-HIGHtransitionofWCLK,data arewrittenintotheEmpty
OffsetMSBRegister. UponthefourthLOW-to-HIGHtransitionofWCLK,data
are written into the Full Offset LSB Register. Upon the fifth LOW-to-HIGH
transitionofWCLK,dataarewrittenintotheFullOffsetMid-ByteRegister. Upon
thesixthLOW-to-HIGHtransitionofWCLK,dataarewrittenintotheFullOffset
MSB Register. The seventh transition of WCLK writes, once again, into the
EmptyOffsetLSBRegister.SeeFigure14,ParallelLoadingofProgrammable
Flag Registers, for the timing diagram for this mode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
not have to occur at one time. One, two or more offset registers can be written
and then by bringing
LDHIGH,writeoperationscanberedirectedtotheFIFO
memory. When
LDissetLOWagain,andWENisLOW,thenextoffsetregister
in sequence is written to. As an alternative to holding
WENLOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling
WEN.
Notethatthestatusofapartialflag(
PAEorPAF)outputisinvalidduringthe
programmingprocess. Fromthetimeparallelprogramminghasbegun,apartial
flag output will not be valid until the appropriate offset word has been written to
theregister(s)pertainingtothatflag.MeasuringfromtherisingWCLKedgethat
achievestheabovecriteria;
PAFwillbevalidaftertwomorerisingWCLKedges
plus tPAF,
PAEwillbevalidafterthenexttworisingRCLKedgesplustPAEplus
tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-
Qn pins when
LD is set LOW and REN is set LOW.
For the IDT72V2101/72V2111, data is read via Qn from the Empty Offset
LSB Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGHtransitionofRCLK, dataarereadfromtheEmptyOffsetMid-Byte
Register. Upon the third LOW-to-HIGH transition of RCLK, data are read from
the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transition of
RCLK, data are read from the Full Offset LSB Register. Upon the fifth LOW-
to-HIGHtransitionofRCLK,dataarereadfromtheFullOffsetMid-ByteRegister.
Upon the sixth LOW-to-HIGH transition of RCLK, data are read from the Full
Offset MSB Register. The seventh transition of RCLK reads, once again, from
the Empty Offset LSB Register. See Figure 15, Parallel Read of Programmable
Flag Registers, for the timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading of
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning
of memory.
Retransmit setup is initiated by holding
RT LOW during a rising RCLK
edge.
REN and WEN must be HIGH before bringing RT LOW. At least two
words, but no more than D - 2 words should have been written into the FIFO
and read from the FIFO between Reset (Master or Partial) and the time of
Retransmit setup. D = 262,144 for the IDT72V2101 and D = 524,288 for the
IDT72V2111 in IDT Standard mode. In FWFT mode, D = 262,145 for the
IDT72V2101 and D = 524,289 for the IDT72V2111.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmitsetupbysetting
EFLOW. Thechangeinlevelwillonlybenoticeable
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
相关PDF资料 |
PDF描述 |
|---|---|
| MAX1082ACUE+T | IC ADC 10BIT 400KSPS 16-TSSOP |
| IDT72V2101L15PF8 | IC FIFO SS 131X18 15NS 64QFP |
| MS27656T15F15PC | CONN RCPT 15POS WALL MNT W/PINS |
| MAX1083ACUE+T | IC ADC 10BIT 300KSPS 16-TSSOP |
| IDT723676L15PF8 | IC FIFO SYNC 16384X36 128QFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V2103L10PF | 功能描述:IC FIFO SUPERSYNCII 10NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2103L10PF8 | 功能描述:IC FIFO SUPERSYNCII 10NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2103L10PFI | 功能描述:IC FIFO SUPERSYNCII 10NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2103L10PFI8 | 功能描述:IC FIFO SUPERSYNCII 10NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2103L15PF | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
发布紧急采购，3分钟左右您将得到回复。