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| 型号： | IDT72V2111L15PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/27页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 512X9 15NS 64QFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.6K（512 x 9） |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2111L15PFI8 |
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13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET (
MRS)
A Master Reset is accomplished whenever the
MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array.
PAE will go LOW, PAF will go HIGH, and
HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with
EF and FF are selected. EF will go LOW and FF will go HIGH.
If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If
LD is LOW during Master Reset, then PAE is assigned a threshold 127
words from the empty boundary and
PAF is assigned a threshold 127 words
from the full boundary; 127 words corresponds to an offset value of 07FH.
Following Master Reset, parallel loading of the offsets is permitted, but not
serial loading.
If
LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and
PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
describing the
LD pin for further details.)
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place.
MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (
PRS)
A Partial Reset is accomplished whenever the
PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array,
PAE goes LOW, PAF goes HIGH, and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then
FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then
OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes.
PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (
RT)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of the
memory.
Retransmitsetupisinitiatedbyholding
RTLOWduringarising RCLKedge.
REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting
EF LOW. The change in level will only be
noticeable if
EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
Retransmit setup requires a LOW on
REN to enable the rising edge of
RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set to
the first location of the RAM array.
When
OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on
REN is
necessary. Reading all subsequent words requires a LOW on
REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (
EF) to indicate
whether or not there are any words present in the FIFO memory. It also uses
the Full Flag function (
FF) to indicate whether or not the FIFO memory has
any free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (
REN)
and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (
OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges,
REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (
REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading
PAE and
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle,
the
FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating
HF flag to LOW.) The Write and Read Clocks can either
be independent or coincident.
WRITE ENABLE (
WEN)
When the
WENinput isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
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相关代理商/技术参数 |
参数描述 |
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| IDT72V2111L20PF | 功能描述:IC FIFO SS 512X9 20NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2111L20PF8 | 功能描述:IC FIFO SS 512X9 20NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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| IDT72V2113L10PF8 | 功能描述:IC FIFO SUPERSYNCII 10NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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