参数资料
型号: IDT72V2113L6PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 19/46页
文件大小: 0K
描述: IC FIFO SUPERSYNCII 6NS 80-TQFP
标准包装: 750
系列: 72V
功能: 同步
存储容量: 4.7Mb(262k x 18)
访问时间: 4ns
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 72V2113L6PF8
26
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then
EF deassertion may be delayed one extra RCLK cycle.
2.
LD = HIGH.
3. First data word latency: tSKEW1 + 1*TRCLK + tREF.
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go high (after one WCLK cycle pus tWFF). If the time between the rising edge
of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the
FF deassertion may be delayed one extra WCLK cycle.
2.
LD = HIGH, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
D0 - Dn
WEN
RCLK
REN
tENH
Q0 - Qn
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
tSKEW1(1)
6119 drw10
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tA
tENS
tDS
tA
DX
tDH
tCLK
tCLKL
DX+1
tDH
FF
tSKEW1(1)
tCLKH
tWFF
NO OPERATION
RCLK
REN
6119 drw11
EF
tCLK
tCLKH
tCLKL
tENH
tREF
tA
tOLZ
tOE
Q0 - Qn
OE
WCLK
tSKEW1(1)
WEN
D0 - Dn
tENS
tENH
tDS
tDHS
D0
1
2
tOLZ
NO OPERATION
LAST WORD
D0
D1
tENS
tENH
tDS
tDH
tOHZ
LAST WORD
tREF
tENH
tENS
tA
tREF
tENS
tENH
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