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参数资料
| 型号： | IDT72V225L15TFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 19/25页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 1024X18 15NS 64QFP |
| 标准包装： | 1,250 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 18.4K（1K x 18） |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V225L15TFI8 |
3
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–D17
DataInputs
I
Data inputs for an 18-bit bus.
RS
Reset
I
WhenRS issetLOW,internalreadandwritepointersaresettothefirstlocationoftheRAMarray,FFand PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
WriteClock
I
WhenWENisLOW,dataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLK,iftheFIFOisnotfull.
WEN
WriteEnable
I
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
RCLK
Read Clock
I
WhenRENisLOW,dataisreadfromtheFIFOonaLOW-to-HIGHtransitionofRCLK,iftheFIFOisnotempty.
REN
Read Enable
I
WhenRENisLOW,dataisreadfromtheFIFOoneveryLOW-to-HIGHtransitionofRCLK. WhenRENisHIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
OE
OutputEnable
I
WhenOEisLOW,thedataoutputbusisactive.IfOE isHIGH,theoutputdatabuswillbeinahigh-impedance
state.
LD
Load
I
When LDisLOW,dataontheinputsD0–D11iswrittentotheoffsetanddepthregistersontheLOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
FL
FirstLoad
I
In the single device or width expansion configuration, FL together with WXI and RXI determine if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, FL is
grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXI
WriteExpansion
I
In the single device or width expansion configuration, WXI together with FL and RXI determine if the mode
Input
isIDTStandardmodeorFWFTmode,aswellas whetherthePAE/PAFflagsaresynchronousorasynchronous.
(SeeTable1.) IntheDaisyChainDepthExpansionconfiguration,WXIisconnectedtoWXO(WriteExpansion
Out) of the previous device.
RXI
Read Expansion
I
In the single device or width expansion configuration, RXI together with FL and WXI, determine if the mode
Input
isIDTStandardmodeorFWFTmode,aswellas whetherthePAE/PAFflagsaresynchronousorasynchronous.
(SeeTable1.) IntheDaisyChainDepthExpansionconfiguration,RXIisconnectedtoRXO(ReadExpansion
Out) of the previous device.
FF/IR
Full Flag/
O
IntheIDTStandardmode,the FFfunctionisselected. FF indicateswhetherornottheFIFOmemoryisfull.In
Input Ready
the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
EF/OR
EmptyFlag/
O
IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
OutputReady
InFWFTmode,theORfunctionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
PAE
Programmable
O
WhenPAEisLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault
Almost-EmptyFlag
offsetatresetis31fromemptyforIDT72V205,63fromemptyforIDT72V215,and127fromemptyforIDT72V225/
72V235/72V245.
PAF
Programmable
O
WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffsetat
Almost-FullFlag
resetis31fromfullforIDT72V205,63fromfullforIDT72V215,and127fromfullforIDT72V225/72V235/72V245.
WXO/HF
WriteExpansion
O
In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the
Out/Half-FullFlag
depthexpansionconfiguration,apulseissentfromWXOtoWXIofthenextdevicewhenthelastlocationinthe
FIFOiswritten.
RXO
Read Expansion
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last
Out
location in the FIFO is read.
Q0–Q17
DataOutputs
O
Data outputs for an 18-bit bus.
VCC
Power
+3.3V power supply pins.
GND
Ground
Seven ground pins.
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