参数资料
型号: IDT72V233L6PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/45页
文件大小: 0K
描述: IC FIFO 1024X18 6NS 80QFP
标准包装: 750
系列: 72V
功能: 异步,同步
存储容量: 18.4K(1K x 18)
数据速率: 166MHz
访问时间: 4ns
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 72V233L6PF8
15
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 3. Programmable Flag Offset Programming Sequence
D/Q8
D/Q0
EMPTY OFFSET REGISTER
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
9
10
11
12
13
14
15
16
D/Q8
D/Q0
FULL OFFSET REGISTER
1
2
3
4
5
6
7
8
D/Q8
D/Q0
EMPTY OFFSET REGISTER
17
18
19
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
9
10
11
12
13
14
15
16
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
17
FULL OFFSET REGISTER
IDT72V293
(2) x9 Bus Width
x9 to x9 Mode
All Other Modes
# of Bits Used:
10 bits for the IDT72V223
11 bits for the IDT72V233
12 bits for the IDT72V243
13 bits for the IDT72V253
14 bits for the IDT72V263
15 bits for the IDT72V273
16 bits for the IDT72V283
17 bits for the IDT72V293
Note: All unused bits of the
LSB & MSB are don't care
# of Bits Used:
9 bits for the IDT72V223
10 bits for the IDT72V233
11 bits for the IDT72V243
12 bits for the IDT72V253
13 bits for the IDT72V263
14 bits for the IDT72V273
15 bits for the IDT72V283
16 bits for the IDT72V293
Note: All unused bits of the
LSB & MSB are don't care
4666 drw06
D/Q8
D/Q0
EMPTY OFFSET REGISTER
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
9
10
11
12
13
14
15
16
D/Q8
D/Q0
FULL OFFSET REGISTER
1
2
3
4
5
6
7
8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
9
10
11
12
13
14
1
5
16
IDT72V223/72V233/72V243/72V253/72V263/
72V273/72V283/72V293
(2) x9 Bus Width
D/Q17
D/Q0
D/Q16
EMPTY OFFSET REGISTER
Data Inputs/Outputs
# of Bits Used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
2nd Parallel Offset Write/Read Cycle
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET REGISTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
Non-Interspersed
Parity
Interspersed
Parity
D/Q17
D/Q0
D/Q16
D/Q8
16
IDT72V223/72V233/72V243/72V253/72V263/72V273/
72V283/72V293 x18 Bus Width
NOTES:
1. When programming the IDT72V293 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72V293 with an output bus
width of x9 and input bus width of x18, 4 read cycles will be required.
2. A total of 6 program/ read cycles will be required for x9 bus width if both the input and output bus widths are set to x9.
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