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参数资料
| 型号： | IDT72V275L15PFI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/25页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 32768X18 15NS 64-TQFP |
| 标准包装： | 90 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 589K（32K x 18） |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 72V275L15PFI |
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
When
WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IRwillgo
LOW allowing a write to occur. The
IR flag is updated by two WCLK
cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the
EF/OR,PAEandHFflags
will not be updated. (Note that RCLK is only capable of updating the
HF flag
to HIGH.) The Write and Read Clocks can be independent or coincident.
READ ENABLE (
REN
REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
When the
RENinputisHIGH,theoutputregisterholdsthepreviousdata
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using
REN. Whenthelast
wordhasbeenreadfromtheFIFO,theEmptyFlag(
EF)willgoLOW,inhibiting
furtherreadoperations.
RENisignoredwhentheFIFOisempty.Onceawrite
isperformed,
EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW
afterthefirstwrite.
RENdoesnotneedtobeassertedLOW. Inordertoaccess
allotherwords,areadmustbeexecutedusing
REN. TheRCLKLOWtoHIGH
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(
OR)
will go HIGH with a true read (RCLK with
REN=LOW),inhibitingfurtherread
operations.
REN is ignored when the FIFO is empty.
SERIAL ENABLE (
SEN
SEN)
The
SENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.
SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGH transition of WCLK. (See Figure 4.)
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functionsthesamewayinbothIDT
Standard and FWFT modes.
OUTPUT ENABLE (
OE
OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
datafromtheoutputregister. When
OEisHIGH,theoutputdatabus(Qn)goes
into a high impedance state.
LOAD (
LD
LD)
This is a dual purpose pin. During Master Reset, the state of the
LDinput
determinesoneoftwodefaultoffsetvalues(127or1,023)forthe
PAEandPAF
flags,alongwiththemethodbywhichtheseoffsetregisterscanbeprogrammed,
parallel or serial. After Master Reset,
LDenableswriteoperationstoandread
operations from the offset registers. Only the offset loading method currently
selected can be used to write to the registers. Offset registers can be read only
in parallel. A LOW on
LD during Master Reset selects a default PAE offset
valueof07FH(athreshold127wordsfromtheemptyboundary),adefault
PAF
offsetvalueof07FH(athreshold127wordsfromthefullboundary),andparallel
loading of other offset values. A HIGH on
LD during Master Reset selects a
default
PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary), a default
PAFoffsetvalueof3FFH(athreshold1,023wordsfrom
the full boundary), and serial loading of other offset values.
AfterMasterReset,the
LDpinisusedtoactivatetheprogrammingprocess
of the flag offset values
PAE and PAF. Pulling LD LOW will begin a serial
loading or parallel load or read of these offset values. See Figure 4, Program-
mable Flag Offset Programming Sequence.
OUTPUTS:
FULL FLAG (
FF
FF/IR
IR
IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF)
functionisselected.WhentheFIFOisfull,
FFwillgoLOW,inhibitingfurtherwrite
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRSorPRS),FFwillgoLOWafterDwritestotheFIFO
(D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285). See Figure
7,WriteCycleandFullFlagTiming(IDTStandardMode),fortherelevanttiming
information.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
are performed after a reset (either
MRS or PRS), IR will go HIGH after
D writes to the FIFO (D = 32,769 for the IDT72V275 and 65,537 for the
IDT72V285) See Figure 9, Write Timing (FWFT Mode), for the relevant timing
information.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
are double register-buffered outputs.
EMPTY FLAG (
EF
EF/OR
OR
OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
functionisselected. WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurther
readoperations. When
EFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
the last word from the FIFO memory to the outputs.
ORgoesHIGHonlywith
a true read (RCLK with
REN=LOW). Thepreviousdatastaysattheoutputs,
indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil
ORgoes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
ORisatripleregister-bufferedoutput.
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相关代理商/技术参数 |
参数描述 |
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| IDT72V275L15PFI8 | 功能描述:IC FIFO SS 32768X18 15NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V275L15TF | 功能描述:IC FIFO SS 32768X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V275L15TF8 | 功能描述:IC FIFO SS 32768X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V275L15TFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X18 15NS 64STQFP |
| IDT72V275L15TFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X18 15NS 64STQFP |
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