参数资料
型号: IDT72V281L20PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/26页
文件大小: 0K
描述: IC FIFO 32768X18 20NS 64QFP
标准包装: 90
系列: 72V
功能: 同步
存储容量: 589K(32K x 18)
数据速率: 50MHz
访问时间: 20ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 托盘
其它名称: 72V281L20PF
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM
65,536 x 9 and 131,072 x 9
PIN CONFIGURATIONS
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
DESCRIPTION (Continued)
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
DC
(1)
VCC
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC
(3)
DNC
(3)
GND
DNC
(3)
DNC
(3)
VCC
DNC
(3)
DNC
(3)
DNC
(3)
GND
DNC
(3)
DNC
(3)
Q8
Q7
Q6
GND
WCLK
PRS
MRS
LD
FWFT/SI
GND
FF
/IR
PAF
HF
V
CC
PAE
EF
/OR
RCLK
REN
RT
OE
Q5
Q4
V
CC
Q3
Q2
GND
Q1
Q0
GND
D0
D1
D2
D3
D4
D5
D6
4513 drw 02
SuperSync FIFOs are particularly appropriate for network, video, telecommu-
nications,datacommunicationsandotherapplicationsthatneedtobufferlarge
amountsofdata.
The input port is controlled by a Write Clock (WCLK) input and a Write
Enable (
WEN) input. Data is written into the FIFO on every rising edge of
WCLK when
WEN is asserted. The output port is controlled by a Read
Clock (RCLK) input and Read Enable (
REN) input. Data is read from the
FIFO on every rising edge of RCLK when
REN is asserted. An Output
Enable (
OE) input is provided for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating
REN and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
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