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参数资料
| 型号： | IDT72V3611L20PQF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 64X36 20NS 132-PQFP |
| 标准包装： | 36 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 2.3K（64 x 36） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 132-BQFP 缓冲式 |
| 供应商设备封装： | 132-PQFP（24.13x24.13） |
| 包装： | 托盘 |
| 其它名称： | 72V3611L20PQF |
4
IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O
Description
PEFB
Port-B Parity Error
O
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as
Flag
(Port B) B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity
trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by
having CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced
HIGH regardlessofthestateoftheB0-B35inputs
PGA
Port-AParity
I
Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity
Generation
generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8,
A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit
of each byte.
PGB
Port-BParity
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated
Generation
is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17,
B18-B26, and B27-B35. The generated parity bitsareoutputinthemostsignificantbitof
each byte.
RST
Reset
I
Toresetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsof
CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the
EF, AE, and FF flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1
andFS0inputstoselectAlmost-FullandAlmost-Emptyflagoffset.
W/RA
Port-AWrite/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a
Select
LOW-to-HIGHtransitionofCLKA. TheA0-A35outputsareinthehigh-impedancestate
when W/RA is HIGH.
W/RB
Port-BWrite/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a
Select
LOW-to-HIGHtransitionofCLKB. TheB0-B35outputsareinthehigh-impedancestate
when W/RB is HIGH.
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| IDT72V3612L12PF | 功能描述:IC FIFO 64X36X2 12NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3612L12PF8 | 功能描述:IC FIFO 64X36X2 12NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3612L12PFG | 功能描述:IC FIFO 64X36X2 12NS 120QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3612L12PQF | 功能描述:IC FIFO 64X36X2 12NS 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3612L15PF | 功能描述:IC FIFO 64X36X2 15NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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