参数资料
型号: IDT72V3641L15PFG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/21页
文件大小: 0K
描述: IC SYNCFIFO 1024X36 15NS 120TQFP
标准包装: 750
系列: 72V
功能: 异步,同步
存储容量: 36.8K(1K x 36)
数据速率: 67MHz
访问时间: 15ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 120-LQFP
供应商设备封装: 120-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 72V3641L15PFG8
12
COMMERCIALTEMPERATURERANGE
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO 512 x 36, 1,024 x 36 and 2,048 x 36
edge that takes the FIFO out of retransmit mode shifts the read pointer used by
the IR and
AF flagsfromtheshadowtothecurrentreadpointer. Ifthechange
of read pointer used by IR and
AF should cause one or both flags to transmit
HIGH, at least two CLKA synchronizing cycles are needed before the flags
reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of IR if it occurs at time tSKEW1 or greater
after the rising CLKB edge (see Figure 13). A rising CLKA edge after the FIFO
is taken out of retransmit mode is the first synchronizing cycle of
AFifitoccurs
at time tSKEW2 or greater after the rising CLKB edge (see Figure 14).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT72V3631/72V3641/72V3651 to
passcommandandcontrolinformationbetweenportAandportB. TheMailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation. ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
to the mail1 register when a port-A Write is selected by
CSA, W/RA,andENA
withMBAHIGH. ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatothe
mail2 register when a port-B Write is selected by
CSB, W/RB, and ENB with
MBB HIGH. Writing data to a mail register sets its corresponding flag (
MBF1
or
MBF2) LOW. Attempted writes to a mail register are ignored while its mail
flagisLOW.
Whentheport-Bdata(B0-B35)outputsareactive,thedataonthebuscomes
fromtheFIFOoutputregisterwhentheport-BMailboxselect(MBB)inputisLOW
and from the Mail1 register when MBB is HIGH. Mail2 data is always present
on the port-A data (A0-A35) outputs when they are active. The Mail1 register
Flag (
MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-
BReadisselectedby
CSB,W/RB,andENBwithMBBHIGH. TheMail2register
Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port-
A Read is selected by
CSA, W/RA, and ENA with MBA HIGH. The data in a
mail register remains intact after it is read and changes only when new data is
writtentotheregister. MailRegisterandMailRegisterFlagtimingcanbefound
in Figure 15 and 16.
相关PDF资料
PDF描述
IDT72V3641L15PF8 IC SYNCFIFO 1024X36 15NS 120TQFP
VI-B61-IV-F2 CONVERTER MOD DC/DC 12V 150W
VE-BNX-MY CONVERTER MOD DC/DC 5.2V 50W
VI-B4Z-IV-B1 CONVERTER MOD DC/DC 2V 60W
IDT723622L15PF8 IC FIFO SYNC 256X36X2 120QFP
相关代理商/技术参数
参数描述
IDT72V3641L15PQF 功能描述:IC SYNCFIFO 1024X36 15NS 132PQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3641L20PF 功能描述:IC SYNCFIFO 1024X36 20NS 120TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3641L20PF8 功能描述:IC SYNCFIFO 1024X36 20NS 120TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3641L20PQF 功能描述:IC SYNCFIFO 1024X36 20NS 132PQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3642L10PF 功能描述:IC FIFO SYNC 3.3V CMOS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF