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| 型号： | IDT72V51453L6BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/50页 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 标准包装： | 1 |
| 类型： | 多队列流量控制 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V51453L6BB |
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17
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
When configuring the IDT72V51433/72V51443/72V51453 devices in de-
fault mode the user simply has to apply WCLK cycles after a master reset, until
SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock
cycles are required for the device to load its internal setup registers. When a
single multi-queue device is used, the completion of device programming is
signaled by the
SENO outputofadevicegoingfromHIGHtoLOW.Note,that
SENImustbeheldLOWwhenadeviceissetupfordefaultprogrammingmode.
When multi-queue devices are connected in expansion mode, the
SENI of
thefirstdeviceinachaincanbeheldLOW.The
SENOofadeviceshouldconnect
to the
SENIofthenextdeviceinthechain.TheSENOofthefinaldeviceisused
to indicate that default programming of all devices is complete. When the final
SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 8, Default Programming.
WRITE QUEUE SELECTION & WRITE OPERATION
The IDT72V51433/72V51443/72V51453 multi-queue flow-control devices
haveupto16queuesthatdatacanbewrittenintoviaacommonwriteportusing
the data inputs, Din, write clock, WCLK and write enable,
WEN. The queue
address present on the write address bus, WRADD during a rising edge on
WCLK while write address enable, WADEN is HIGH, is the queue selected for
writeoperations.Thestateof
WENisdon’tcareduringthewritequeueselection
cycle. The queue selection only has to be made on a single WCLK cycle, this
will remain the selected queue until another queue is selected, the selected
queue is always the last queue selected.
The write port is designed such that 100% bus utilization can be obtained.
This means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed. When a new queue
is selected for write operations the address for that queue must be present on
the WRADD bus during a rising edge of WCLK provided that WADEN is HIGH.
A queue to be written to need only be selected on a single rising edge of WCLK.
Allsubsequentwriteswillbewrittentothatqueueuntilanewqueueisselected.
Aminimumof2WCLKcyclesmustoccurbetweenqueueselectionsonthewrite
port. On the next WCLK rising edge the write port discrete full flag will update
to show the full status of the newly selected queue. On the second rising edge
of WCLK, data present on the data input bus, Din can be written into the newly
selected queue provided that
WENisLOWandthenewqueueisnotfull.The
cycleofthequeueselectionandthenextcyclewillcontinuetowritedatapresent
on the data input bus, Din into the previous queue provided that
WENisactive
LOW.
If
WENisHIGH,inactiveforthese2clockcycles,thendatawillnotbewritten
in to the previous queue.
Ifthenewlyselectedqueueisfullatthepointofitsselection,thenwritestothat
queue will be prevented, a full queue cannot be written into.
In the 16 queue multi-queue device the WRADD address bus is 7 bits wide.
The least significant 4 bits are used to address one of the 16 available queues
within a single multi-queue device. The most significant 3 bits are used when
a device is connected in expansion mode, up to 8 devices can be connected
in expansion, each device having its own 3 bit address. The selected device
istheoneforwhichtheaddressmatchesa3bitIDcode,whichisstaticallysetup
on the ID pins, ID0, ID1, and ID2 of each individual device.
Note,theWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag
bus strobe), to address the almost full flag bus sector during direct mode of
operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
9, Write Queue Select, Write Operation and Full flag Operation and Figure
11, Full Flag Timing Expansion Mode for timing diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[6:0]
Operation WCLK WADEN
FSTR
WRADD[6:0]
Write Queue
Select
10
01
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(4 bits = 16 Queues)
654
3 2
1 0
765 4 3 2
0
Device Select
(Compared to
ID0,1,2)
X X X
Sector
Address
PAFn Sector
Select
Q0 : Q7
→ PAF0 : PAF7
Sector
Address
Queue Status on
PAFn Bus
0
1
Q8 : Q15
→ PAF0 : PAF7
5939 drw05
1
X
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| IDT72V51453L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51453L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51453L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51453L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51456L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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