- 您现在的位置：买卖IC网 > PDF目录2077 > IDT72V73263BB (IDT, Integrated Device Technology Inc)IC DGTL SW 16384X16384 208-BGA PDF资料下载
参数资料
| 型号： | IDT72V73263BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/36页 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 16384X16384 208-BGA |
| 标准包装： | 12 |
| 系列： | 72V |
| 类型： | 多路复用器 |
| 电路： | 8 x 1:1 |
| 电压电源： | 单电源 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BGA |
| 供应商设备封装： | 208-PBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V73263BB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
3
INDUSTRIAL TEMPERATURERANGE
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
PIN DESCRIPTION
A0-A15
Address0-15
I
*See PBGA
Theseaddresslinesaccessallinternalmemories.
TableBelow
BEL
Byte Enable LOW
I
L4
In synchronous mode, this input will enable the lower byte (D0-7) on to the data bus.
C32i
Clock
I
A1
Serialclockforshiftingdatain/outontheserialdatastreams. Thisinputacceptsa
32.768MHz clock.
CS
Chip Select
I
E1
Active LOW input used by a microprocessor to activate the microprocessor port of the
device.
D0-15
DataBus0-15
I/O
*See PBGA
Thesepinsarethedatabusofthemicroprocessorport.
TableBelow
DS
DataStrobe
I
This active LOW input works in conjunction with CS to enable the read and write
D4
operations. ThisactiveLOWinputsetsthedatabuslines(D0-D15).
DTA/BEH
DataTransfer
I/O
Inasynchronousmodethispinindicatesthatadatabustransferiscomplete.Whenthe
Acknowledgment
K2
bus cycle ends,this pin drives HIGH and then High-Z allowing for faster bus cycles
Active LOW Output
with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level
when the pin is High-Z. When the device is in /Byte Enable HIGH synchronous
bus mode, this pin acts as an input and will enable the upper byte (D8-15) on to the
databus.
F32i
FramePulse
I
B1
Thisinputacceptsandautomaticallyidentifiesframesynchronizationsignalsformatted
according to ST-BUS and GCI specifications.
GND
*See PBGA
Ground.
TableBelow
ODE
OutputDriveEnable
I
A3
Thisistheoutputenablecontrol fortheTXserialoutputs.WhenODEinputisLOWand
the OSB bit of the CR register is LOW, all TX outputs are in a High-Impedance state. If
this input is HIGH, the TX output drivers are enabled. However, each channel may
still be put into a High-Impedance state by using the per channel control bits in the
Connection Memory HIGH.
RX0-63
RX Input 0 to 63
I
*See PBGA
Serial data Input Stream. These streams may have data rates of 2.048Mb/s,
TableBelow
4.096Mb/s,8.192Mb/s,16.384Mb/s,or32.768Mb/sdependingupontheselectioninReceive
DataRateSelectionRegister(RDRSR).
RESET
Device Reset:
I
A2
This input (active LOW) puts the device in its reset state that clears the device internal
counters,registersandbringsTX0-63andmicroportdataoutputstoaHigh-Impedance
state. The RESET pin must be held LOW for a minimum of 20ns to reset the device.
R/W
Read/Write
I
E2
Thisinputcontrolsthedirectionofthedatabuslines(D0-D15)duringamicroprocessor
access.
S/A
Synchronous/
I
C1
Thisinputwillselectbetweenasynchronousmicroprocessorbustimingandsynchronous
Asynchronous
microprocessor bus timing. In synchronous mode, DTA/BEHacts as the BEH input and is
Bus Mode
used in conjunction with BELto output data on the data bus. In asynchronous bus mode,
BEL is tied LOW and DTA/BEH acts as the DTA, data bus acknowledgment output.
TCK
Test Clock
I
D2
Provides the clock to the JTAG test logic.
TDI
TestSerialDataIn
I
C3
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH
by an internal pull-up when not driven.
TDO
TestSerialDataOut
O
D1
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in
High-ImpedancestatewhenJTAGscanisnotenabled.
TMS
TestModeSelect
I
C2
JTAGsignalthatcontrolsthestatetransitionsoftheTAPcontroller.Thispinispulled
HIGH by an internal pull-up when not driven.
TRST
TestReset
I
D3
AsynchronouslyinitializestheJTAGTAPcontrollerbyputtingitintheTest-Logic-
Reset state. This pin is pulled by an internal pull-up when not driven. This pin should
be pulsed LOW on power-up, or held LOW, to ensure that the device is in the normal
functionalmode.
SYMBOL
NAME
I/O
PBGA
DESCRIPTION
PIN NO.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT72V73273BBG | IC DGTL SW 32768X32768 208-BGA |
| IDT72V845L10PF | IC FIFO SYNC 4096X18 128QFP |
| IDT72V851L10TFG | IC FIFO 8192X9 DUAL SYNC 64TQFP |
| IDT72V85L15PAG | IC FIFO ASYNCH 4096X18 56TSSOP |
| IDT72V8980PVG | IC DGTL SW 256X256 48-SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V73273BB | 功能描述:IC DGTL SW 32768X32768 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - 信号开关，多路复用器，解码器 系列:72V 标准包装:48 系列:74VHC 类型:多路复用器 电路:4 x 2:1 独立电路:1 输出电流高，低:8mA，8mA 电压电源:单电源 电源电压:2 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:管件 |
| IDT72V73273BBG | 功能描述:IC DGTL SW 32768X32768 208-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 信号开关，多路复用器，解码器 系列:72V 标准包装:48 系列:74VHC 类型:多路复用器 电路:4 x 2:1 独立电路:1 输出电流高，低:8mA，8mA 电压电源:单电源 电源电压:2 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:管件 |
| IDT72V801L10PF | 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V801L10PF8 | 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V801L10PFG | 功能描述:IC FIFO 256X9 SYNC DUAL 64TQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
发布紧急采购，3分钟左右您将得到回复。