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参数资料
| 型号： | IDT7381L40J8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 位片处理器 |
| 英文描述： | 16-BIT, BIT-SLICE MICROPROCESSOR, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 15/17页 |
| 文件大小： | 257K |
| 代理商： | IDT7381L40J8 |
7
IDT7381
16-BIT CASCADABLE ALU
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%, TA = 0°C to +70°C) - (Cont'd.)
NOTES:
1. Only for FTF = 0.
2. Minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns.
Minimum Set-up and Hold Times Relative to Clock (CLK)
IDT7381L25
IDT7381L30
IDT7381L40
IDT7381L55
Input
Set-up
Hold
Set-up
Hold
Set-up
Hold
Set-up
Hold
Unit
FTAB = 0, FTF = X
A0–A15, B0–B15
60
8
0
ns
C0 (1)
16
0
16
0
16
0
21
0
ns
I0–2, RS0, RS1 (1)
24
0
29
0
32
0
44
0
ns
ENA, ENB, ENF
60
8
0
ns
FTAB = 1, FTF = 0
A0–A15, B0–B15
16
0
25
0
28
0
35
0
ns
C0
16
0
16
0
16
0
21
0
ns
I0–2, RS0, RS1
24
0
29
0
32
0
44
0
ns
ENF
60
8
0
ns
Minimum Clock Cycle Times and Pulse Widths
Parameter
IDT7381L25
IDT7381L30
IDT7381L40
IDT7381L55
Unit
Clock LOW Time
6
8
10
14
ns
Clock HIGH Time
6
8
10
14
ns
Clock Period
20
25
34
43
ns
Maximum Output Enable/Disable Times
Parameter
IDT7381L25
IDT7381L30
IDT7381L40
IDT7381L55
Unit
Enable Time
10
15
18
20
ns
Disable Time
10
15
18
20
ns
相关PDF资料 |
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|---|---|
| IDT7383G | 32-BIT, BIT-SLICE MICROPROCESSOR, CPGA68 |
| IDT7381J | 32-BIT, BIT-SLICE MICROPROCESSOR, PQCC68 |
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| IDT7383FF | 32-BIT, BIT-SLICE MICROPROCESSOR, CQFP68 |
| IDT7383L55G | 16-BIT, BIT-SLICE MICROPROCESSOR, CPGA68 |
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