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参数资料
| 型号： | IDT7381L40J8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 位片处理器 |
| 英文描述： | 16-BIT, BIT-SLICE MICROPROCESSOR, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 8/17页 |
| 文件大小： | 257K |
| 代理商： | IDT7381L40J8 |
16
COMMERCIALTEMPERATURERANGE
IDT7381
16-BIT CASCADABLE ALU
Pulse
Generator
R T
D.U .T.
V CC
V IN
C L
V OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIM ING
INPUT
ASYNCH R ONOUS C ONTROL
PRES ET
CLEA R
ETC.
SYNC HRON OUS CONT ROL
tSU
tH
tREM
tSU
tH
PRES ET
CLEA R
CLOC K ENABLE
ETC.
HIGH -LOW -HIGH
PULS E
LOW -HIGH-LOW
PULS E
tW
1.5V
SAM E PHA SE
INPUT TR ANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOS ITE PHASE
INPUT TR ANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NOR MA LLY
LOW
OUTPUT
NOR MA LLY
HIGH
SW ITC H
CLOSE D
SW ITC H
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENAB LE
DISABLE
VOH
TEST WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
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