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参数资料
| 型号： | IDT74ALVC16835PAG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封装： | TSSOP-56 |
| 文件页数： | 2/6页 |
| 文件大小： | 72K |
| 代理商： | IDT74ALVC16835PAG |
INDUSTRIALTEMPERATURERANGE
2
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance
VIN = 0V
7
9
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
±50
mA
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
Pin Names
Description
OE
3-State Output Enable Inputs (Active LOW)
CLK
Register Input Clock
LE
Latch Enable (Transparent LOW)
A x
Data Inputs
Y x
3-State Outputs
N C
No Internal Connection
PIN DESCRIPTION
TSSOP/ TVSOP
TOP VIEW
FUNCTION TABLE(1)
Inputs
Outputs
OE
LE
CLK
Ax
Yx
HX
X
Z
LH
X
L
LH
X
H
LL
↑
LL
↑
HH
LL
H
X
Y
0
(2)
LL
L
X
Y
0
(3)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established,
provided that CLK is HIGH before LE went HIGH.
3. Output level before the indicated steady-state input conditions were established.
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
GND
25
26
27
28
32
31
30
29
GND
NC
A1
NC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VCC
A16
A17
A18
GND
VCC
CLK
GND
VCC
GND
OE
LE
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相关代理商/技术参数 |
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| IDT74ALVC16835PFG | 功能描述:IC UNIV BUS DVR 18BIT 56TVSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVC 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
| IDT74ALVC16835PFG8 | 功能描述:IC UNIV BUS DVR 18BIT 56TVSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVC 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
| IDT74ALVC1G00DY | 制造商:INT_DEV_TECH 功能描述: |
| IDT74ALVCF162835APA | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVCF 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
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