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| 型号： | IDT74ALVCHR16601PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封装： | TVSOP-56 |
| 文件页数： | 1/7页 |
| 文件大小： | 73K |
| 代理商： | IDT74ALVCHR16601PF |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCHR16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
1
JUNE 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4491/2
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
Balanced Output Drivers: ±12mA
Low Switching Noise
B1
A1
LEAB
CLKBA
OEBA
LEBA
CLKAB
TO 17 OTHER CHANNELS
CE
1D
C1
CE
1D
C1
CLK
CLKENAB
OEAB
CLKENBA
27
29
30
2
28
55
56
1
3
54
CLK
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The transceiver combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the data
is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output
enable OEAB is active low. When OEAB is low, the outputs are active. When
OEAB is high, the outputs are in the high-impedance state.
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,LEBA,CLKBA
and CLKENBA.
The ALVCHR16601 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive±12mA at the designated threshold levels.
The ALVCHR16601 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
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| IDT74ALVCHS162830DF | 功能描述:IC ADD DVR 1-2BIT TRI-ST 80TVSOP RoHS:否 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74ALVCHS 标准包装:1,000 系列:74ABT 逻辑类型:寄存收发器，非反相 元件数:1 每个元件的位元数:8 输出电流高，低:32mA，64mA 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) |
| IDT74ALVCHS162830DF8 | 功能描述:IC ADD DVR 1-2BIT TRI-ST 80TVSOP RoHS:否 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74ALVCHS 标准包装:1,000 系列:74ABT 逻辑类型:寄存收发器，非反相 元件数:1 每个元件的位元数:8 输出电流高，低:32mA，64mA 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) |
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