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参数资料
| 型号： | IDT74FCT2541CTD |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封装： | CERDIP-20 |
| 文件页数： | 8/9页 |
| 文件大小： | 183K |
| 代理商： | IDT74FCT2541CTD |
IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
6.8
8
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2565 drw 10
2565 drw 14
2565 drw 11
2565 drw 12
2565 drw 13
Pulse
Generator
R T
D.U.T.
V CC
VIN
C L
VOUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
2565 drw 14
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
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