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| 型号： | IDT74LVCH646APG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封装： | TSSOP-24 |
| 文件页数： | 1/7页 |
| 文件大小： | 96K |
| 代理商： | IDT74LVCH646APG |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVCH646A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
TO SEVEN OTHER CHANNELS
B1
1
D
C1
1
D
C1
A1
SAB
CLKAB
SBA
OE
CLKBA
21
23
22
1
2
4
20
DIR
3
One of eight Channels
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
OCTOBER 1999
1999
Integrated Device Technology, Inc.
DSC-4499/-
c
IDT74LVCH646A
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The LVCH646A device consists of bus-transceiver circuits, D-type flip-
flops, and control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal registers. Data on the A or
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
– Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.3V to 3.6V, Extended Range
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
3.3V CMOS OCTAL BUS
TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FUNCTIONAL BLOCK DIAGRAM
B bus is clocked into the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Output-enable (OE) and direction-control (DIR) inputs control the trans-
ceiver functions. In the transceiver mode, data present at the high-imped-
ance port is stored in either register or in both. The select-control (SAB and
SBA)inputscan multiplexstoredandreal-time(transparentmode)data.DIR
determines which bus receives data when OE is low. In the isolation mode
(OE high), A data is stored in one register and B data can be stored in the
other register. When an output function is disabled, the input function is still
enabled and can be used to store and transmit data. Only one of the two
buses, A or B, can be driven at a time.
The LVCH646A has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
To ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVCH646A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
Drive Features for LVCH646A:
– High Output Drivers:
±24mA
– Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
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